Cadence Allegro FPGA System Planner
Cadence Allegro FPGA System Planner provides an FPGA-PCB co-design environment that automates the creation of optimum, correct-by-construction pin assignment.

The Allegro® FPGA System Planner offers a unique set of capabilities to address the challenges engineers face when designing one or more FPGAs in their PCB. These challenges include creating the initial pin assignment, integrating with the schematic, and ensuring that the device is routable on the board. Often the pin assignment for these FPGAs is done manually at a pin-by-pin level in an environment that is unaware of the placement of critical PCB components that are connected to FPGAs. The FPGA System Planner is a complete, scalable solution that eliminates manual processes and replaces them with pin assignment synthesis.

By enabling placement-aware pin assignment synthesis—which is FPGA device rules accurate—the Allegro FPGA System Planner offers a unique set of capabilities for FPGA-PCB co-design. It provides a floorplan view to place components in the FPGA system and allows users to specify connectivity between components within the FPGA sub-system at a higher level through interface definitions. With its placement aware-pin assignment synthesis, the Allegro FPGA System Planner enables users to explore their FPGA-based architecture and to create an optimum correct-by-construction pin assignment for either production or prototype designs that use FPGAs. This unique placement-aware pin assignment approach eliminates unnecessary physical design iterations that are inherent in manual approaches while shortening the design cycle time.

Benefits:
  • Scalable FPGA-PCB co-design solution from OrCAD® Capture to Allegro GXL
  • Shortens time for optimum initial pin assignment, accelerating PCB design schedules
  • Accelerates integration of FPGAs with Cadence® PCB design creation environments
  • Eliminates unnecessary, frustrating design iterations during the PCB layout process
  • Eliminates unnecessary physical prototype iterations due to FPGA pin assignment errors
  • Reduces PCB layer count through placement-aware pin assignment and optimization
  • Enables interface-based connectivity definition for the FPGA system 
  • Enables placement-aware pin assignment synthesis that is FPGA-DRC accurate
  • Allows architectural exploration for FPGA system
  • Speeds ASIC prototyping using FPGAs
FPGA Model Library
A library of device-accurate FPGA models is included in Allegro FPGA System Planner. This library incorporates pin assignment rules...
Interface Definitions
Interface definitions allow users to specify connectivity between components within the FPGA sub-system at a higher level.
Powerful DRC Engine
A built-in DRC engine incorporates the rules provided by FPGA vendors for pin assignment, reference voltages, and terminations.
Pin Assignment Synthesis
Placement-aware pin assignment synthesis shortens the time required to create pin assignment for a large number of FPGAs.
Integration with PCB and FPGA Design Tools
In addition to integration with Cadence PCB design tools, the Allegro FPGA System Planner communicates seamlessly with FPGA design tools.
DescriptionType
The Cadence® Allegro® FPGA System Planner addresses the challenges that engineers encounter when designing one or more large-pin-count FPGAs on the PCB board.
DataSheet (PDF)
Current solutions for application-specific integrated circuit (ASIC) prototyping limit the designers choices. Cadence® Allegro® FPGA System Planner offers a simplified and more flexible approach to ASIC prototyping.
Application Note
Allegro FPGA System Planner helped JDSU achieve a 30% to 40% time savings in their front-end design process. In addition, they realized a 50% time reduction in routing high-speed signals.
Customer Success Story
In this paper Cadence offers recommendations for power-supply connections, pin selections and assignments, and other tips and methodologies to help customers design high-quality FPGA-based systems.
DataSheet (PDF)
Active-HDL is an integrated FPGA Design and Simulation solution, with design entry, a high-performance mixed-language simulator and an easy-to-use, multi-vendor FPGA flow manager.
DataSheet (PDF)
The Cadence® OrCAD® FPGA System Planner addresses the challenges that engineers encounter when designing large-pin-count FPGAs on the PCB board.
DataSheet (PDF)
With the help of Cadence Software, VeriSilicon shortened their FPGA-based ASIC prototype development time by 75% and completed optimal pin assignment in one week vs. at least one month previously.
Customer Success Story
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