Intuitive PCB Editor
At the heart of Allegro PCB Designer is the PCB editor—an intuitive, easy-to-use, constraint-driven environment for creating and editing simple to complex PCBs.

Its extensive feature set addresses a wide range of design and manufacturability challenges such as floorplanning, etch creation, placement, and routing. For floorplanning PCB designer includes placement replication for accelerating placement of the design. Its powerful shape-based shove, hug interactive etch creation and editing establishes a highly productive interconnect environment and provides real-time, heads-up displays of length and timing margins. Another highlight is the dynamic shape capability. It offers real-time copper pour plowing & healing functionality during placement and routing iterations.

Powerful Routing Tools
The routing feature of the PCB editor provides powerful, interactive capabilities that deliver controlled automation to maintain user control, while maximizing routing productivity.

Real-time, shape based, any-angle, push/shove routing enables users to choose from “shove preferred,” “hug-preferred,” or “hug only” modes. During etch editing, the designer can view a real-time, graphical heads-up display of how much timing slack remains for interconnect that has high-speed constraints. Interactive routing also enables group routing on multiple nets and interactive tuning of nets with high-speed length or delay constraints.

Create Reliable Manufacturing Data
A full suite of phototooling, bare-board fabrication, and test outputs, including Gerber 274x, NC drill, and bare-board test in a variety of formats, can be generated.

More importantly, Cadence supports the industry initiative toward Gerberless manufacturing through its Valor ODB++ interface that also includes the Valor Universal Viewer. The ODB++ data format creates accurate and reliable manufacturing data for high-quality Gerberless manufacturing.

Design Reuse Module
Superior placement replication technology within Allegro PCB Designer allows users to quickly place and route multiple similar circuits in a design.

It allows users to create a template using one instance of placed and routed circuit that can be applied to other instances within the design. The saved placement template can be used with other designs where similar circuits are used. When replicating placement, users can flip or mirror the circuit from top layer to bottom layer. All associated etch elements, including blind buried vias, are mapped to correct layers when circuit is moved from top layer to bottom layer.

Constraint-Driven Design
At the heart of Allegro PCB Designer is a PCB editor—an intuitive, easy-to-use, constraint-driven environment for creating and editing simple to complex PCBs.

Its extensive feature set addresses a wide range of design and manufacturability challenges:

• A powerful set of floorplanning and placement tools including placement replication for accelerating placement of the design
• Powerful shape-based shove, hug interactive etch creation, editing establishes a highly productive interconnect environment while providing real-time, heads-up displays of length and timing margins
• Dynamic shape capability offers real-time copper pour plowing & healing functionality during placement and routing iterations

The PCB editor can also generate a full suite of phototooling, bare-board fabrication, and test outputs, including Gerber 274x, NC drill, and bare-board test in a variety of formats.

A constraint management system displays physical and spacing rules. Each worksheet provides a spreadsheet interface that enables the user to define, manage, and validate the different rules in a hierarchical fashion. This powerful application allows designers to graphically create, edit, and review constraint sets as graphical topologies that act as electronic blueprints of an ideal implementation strategy. Once the constraints are present in the database, they are used to drive the placement and routing processes for constrained signals. The constraint management system is completely integrated with the PCB editor.

Analog/RF Design Option
The Allegro PCB Designer through its Analog/RF Design Option offers a mixed signal design environment,...

from schematic to layout with back annotation, proven to increase RF design productivity up to 50%. It allows engineers to create, integrate, and update analog/ RF/ microwave circuits with digital/analog circuits in the Allegro PCB Design environment. With its rich layout capability and powerful interfaces with RF simulation tools, it allows engineers to start RF design from Allegro Design Authoring, Allegro PCB Designer, or Agilent ADS.

High-Speed Option
High-speed routing constraints and algorithms handle differential pairs, net scheduling, timing, crosstalk, layer set routing, and the special geometry requirements demanded by today’s high-speed circuits.

The autorouting algorithms intelligently handle routing around or through vias, and automatically conform to defined length or timing criteria. Automatic net shielding is used to reduce noise on noise sensitive nets. Separate design rules may be applied to different regions of the design; for example, you can specify tight clearance rules in the connector area of a design and less stringent rules elsewhere.

Miniaturization Option
The Miniaturization Option is for designers looking to implement a buildup PCB technology using high-density interconnect (HDI).

It offers a proven constraint-driven HDI design flow with a comprehensive set of design rules for all different styles of HDI designs, from a hybrid buildup/core combination to a complete buildup process like ALIVH. In addition, it includes automation for adding HDI to shorten the time to create designs that are correct-by-construction.

Reducing end product size can be accomplished in many different ways. One of the approaches is to embed packaged components on inner layers. The Miniaturization Option offers constraint driven embedded component placement and routing. It supports traditional direct attach as well as new indirect attach techniques. Additionally it offers the ability to create and manage cavities on layers specified for embedding components.

Design Publisher Option
The Design Publisher Option converts Allegro PCB Design layouts to content-rich Adobe Portable Document Format (PDF) files,...

creating a secure, single-file representation of the design. The PDF files provide navigation through the layers as well as access to design attributes and constraints, making them ideal for design reviews. Intellectual property (IP) is protected through access controls that allow you to decide what design data is published for review.

Design Planning Option
The Deign Planning Option captures a designer’s specific routing intent and acts upon it; an ability other CAD tools lack.

The Global Route Environment provides the technology and methodology to capture as well as adhere to a designer’s intent. Through the interconnect flow planning architecture and the global route engine, users can put their experience and design intent into a tool that understands what they want—natively.

Users create abstracted interconnect data (through the interconnect flow planning architecture) and can quickly converge on a solution and validate it with the global route engine. The interconnect abstraction reduces the number of elements the system has to deal with, from potentially tens of thousands down to hundreds, resulting in a significant reduction in the manual interaction required. This significant simplification over current design tools means users converge on a successful interconnect solution far faster and more easily than ever before, reducing design cycle time through increased efficiency and productivity.

Router Option
The Router Option provides designers with advanced routing capabilities to handle complex interconnect with automated technology.

Manufacturing algorithms provide a spreading capability that automatically increases conductor clearances on a space-available basis. Mitered corners and test points can be added throughout the routing process. The manufacturing algorithms automatically use the optimal setback range, starting from the largest to the smallest value. Test point insertion automatically adds testable vias or pads as test points. Testable vias can be probed on the front, back, or both sides of the PCB, supporting both single side and clamshell testers.

High-speed routing constraints and algorithms handle differential pairs, net scheduling, timing, crosstalk, layer set routing, and the special geometry requirements demanded by today’s high-speed circuits. The autorouting algorithms intelligently handle routing around or through vias, and automatically conform to defined length or timing criteria. Separate design rules may be applied to different regions of the design; for example, you can specify tight clearance rules in the connector area of a design and less stringent rules elsewhere.

Concurrent Team Design
Globally dispersed design teams are on the rise, which compounds the challenge of shortening design cycle times.

Manual workarounds that address multi-user issues are time-consuming, slow, and prone to error. Allegro PCB Design Partitioning technology provides a multi-user, concurrent design methodology for faster time to market and reduced layout time. Multiple designers working concurrently on a layout share access to a single database, regardless of team proximity. Designers can partition designs into multiple sections or areas for layout and editing by several design team members. Designs can be partitioned vertically (sections) with soft boundaries or horizontally (layers). As a result, each designer can see all partitioned sections and update the design view for monitoring the status and progress of other users’ sections. Such partitioning can dramatically reduce over-all design cycles and accelerate the design process.