Allegro Sigrity

Cadence Sigrity Technologies provide the signal integrity and power analysis solutions needed for system-level verification and interface compliance. Signoff with confidence.

Increases in IC speed, faster data transmission rates, smaller geometries, and an emphasis on optimization have made power and signal integrity issues tightly connected. To address these issues, designers need advanced power integrity and power-aware signal integrity tools. This level of technology allows designers to see the complete picture and achieve signoff-level verification through their analysis. Mistakes are not an option on projects this advanced, that's why designers choose proven Sigrity™ solutions, from Cadence®.

By adopting Sigrity solutions, designers can perform three major tasks of the design verification process:

  • Analyze the complete power delivery system across chips, packages, and boards.
  • Perform system-level signal integrity (SI) analysis, including simultaneous switching noise analysis of high-speed signal transmissions.
  • Utilize the advanced physical design tools for single and multi-chip packages, state-of-the-art 3D packages, and systems-in-package (SiPs).
Award Winning Solutions

  • Power Aware SI analysis helps understand the complete picture
  • Use Power Deliver Network (PDN) analysis to optimize for the best cost/performance ratio
  • Proven Sigrity Technology from a large, stable partner, Cadence
  • Extract very large, complicated DDR3 and DDR4 networks and simulate using power-aware IBIS models
  • Perform electrical and thermal co-simulation
  • Ability to support large designs that include both package and board structures
  • Flexible visualization options including 3D fly-through
  • Readily used in Cadence, Mentor, Zuken, and Altium flows, accepting a mix of CAD databases where needed for multi-structure design support
Power Integrity
Cadence power integrity (PI) solutions, based on Sigrity technology, provide signoff-level accuracy for AC and DC power analysis of PCBs and IC packages. Each tool seamlessly interfaces with Cadence Allegro® PCB and IC packaging physical design solutions.

Power Integrity
Advanced signal integrity, power integrity, and design-stage EMI solutions help designers guarantee results. Sigrity tools support S-parameter model extraction and provide robust frequency domain simulation for entire IC package and PCB designs.

Key Features
  • Proven through use on thousands of production designs
  • Highly accurate, even for designs with unusual plane structures
  • Fast throughput with multi-processor support and options for distributed computing
  • Ability to support large designs that include both package and board structures
  • Flexible visualization options including 3D fly-through
  • Extensive user control of port selection and abstraction management
  • Strong HSPICE flow support

DC Power Simulation
Sigrity tools help designers achieve efficient DC signoff for IC package and PCB designs, with electrical/thermal co-simulation to maximize accuracy. With these tools you can quickly pinpoint IR drop and current hotspots, and automatically find best remote sense locations.

Key Features
  • Pinpoint IR drop and voltage distribution issues
  • Automatically identify preferred voltage regulator module (VRM) sense line locations
  • Locate current hotspots that can lead to reliability problems
  • Identify difficult-to-locate highly resistive routing neck-downs and find the one via among thousands that will fail under stress
  • Co-simulates electrical and thermal performance to identify interrelated voltage and temperature impacts
  • Consider what-if improvement options with a unique block-diagram results view, a range of visualization options, and interactive geometry editing
Sigrity technology enables design teams to balance decoupling capacitor (decap) cost and performance for PCBs and IC packages. Decap cost savings of 15% to 50% are typical. These tools support pre and post-layout decap studies, identify impedance issues, and suggests placement locations for EMI decaps.

Key Features
  • Automatically selects and places decoupling capacitors
  • Eliminates decap over-design for PCBs and IC packages
  • Reduces PDS cost for new designs and post-production products
  • Develops effective decap guidelines for packaged components
  • Recaptures design area by eliminating unnecessary decaps
  • Assesses PDS cost vs. performance tradeoffs interactively
  • Optimizes a PDS across the board/package interface
  • Creates lowest cost/best performance decap placement tables
  • Identifies both the number and locations for EMI decaps
Power-Aware SI
Cadence power-aware signal integrity (SI) tools, based on Sigrity technology, provide signoff-level accurate SI analysis for PCBs and IC packages. Signoff-level SI accuracy of signals with frequency higher than one gigahertz must consider the signals and the power/ground network that enables the current return path. Cadence Power-Aware SI tools interface seamlessly with Cadence Allegro PCB and IC packaging physical design tools to create a complete power-aware design and SI analysis solution.
    Parallel and Serial Link Verification
    A comprehensive and automated signal integrity environment for the accurate assessment of high-speed chip-to-chip system designs. Ensures robust parallel bus and serial link interface implementations.

    Key Features
    • End-to-end analysis solution for source-synchronous parallel interfaces such as DDRx memory
    • Fully account for impacts associated with non-ideal power delivery system characteristics
    • Graphical outputs and post-processing options give insight for rapid system improvements
    • Chip-to-chip analysis of high-speed SerDes designs such as PCIe, HDMI, SFP+, Xaui, Infiniband, SAS, SATA, USB, and more
    • Identify crosstalk issues and show the effectiveness of chip-level clock and data recovery (CDR) techniques
    • Full-channel simulations including millions of bits of data confirm overall bit-error rate (BER)

    Signal and Power Integrity
    A complete PCB/package layout-based time domain EM simulation tool for signal integrity, power integrity, and design-stage EMI analysis. Supports advanced layout checking for design signoff and debug.

    Key Features
    • Performs time domain analysis to confirm that designs meet specified targets
    • Understands complex voltage noise propagation including return path discontinuities
    • Simulates simultaneous switching noise (SSN) and identifies improvement options
    • Assesses various decoupling capacitor implementations
    • Determines the impact of variations in stack-up, plane geometries, and I/O configurations
    • Identifies package and board resonance and radiation harmonics
    • Observes where noise is generated, identifies how it propagates, and determines if it stays within targeted levels
    • Provides streamlined workflows for layout-based DDR SSN simulation and layout-based electrical performance checks
    • Generates effective pre-layout guidelines and understands the impact of variances as the design progresses

    Broadband SPICE
    A combination of S-parameter checking, tuning, and extraction capability to convert N-port network parameters to efficient SPICE-compatible circuits that can be used in time domain simulations.

    Key Features
    • Creates SPICE-equivalent circuits from network parameters
    • Bridges frequency and time domains
    • Generates models for DC through broadband frequencies
    • Extracts network models with multiple resonance points
    • Models a broad range of structures including IC packages, RF components, PCBs, cables, and connectors
    • Assesses real-world situations such as parallel traces traversing a split plane, spiral inductors, and return path discontinuities
    • Generates a very high order, but numerically stable, model for complex network responses
    • Enables analysis of PI/SI issues such as what-if optimization of power delivery system performance and simultaneous switching output simulation
    Transistor-to-behavioral Model Conversion
    Transistor-to-behavioral model conversion is an efficient way to create accurate models for SSO and other simulations. These models run an order of magnitude faster than the original transistor models.

    Key Features
    • Converts transistor driver models into highly accurate behavioral models
    • Automatically generates IBIS 3.2, 4.2, or 5.0 models as well as new accuracy-enhanced models
    • Dramatically improves chip/system co-simulation efficiency and capacity
    • Identifies the root cause of SI/PI issues and verifies fixes
    • Produces models for full bus simulations with Sigrity SystemSI or SPEED2000
    • Improves accuracy of results in flows that use HSPICE and third-party simulators
    • Verifies behavioral model accuracy vs. the original transistor model with an included time domain simulation wizard
    • Enables practical co-simulation flows that include broadband chip-package-board models
    Layout Checking for SI Performance
    This webcast focuses on Sigrity's streamlined design flow for PCB signal integrity performance checking. This new approach provides more comprehensive information than physical DRC checks alone, and can be performed much more rapidly than time-domain simulation flows.

    Watch Now
    EMI Analysis and Optimization
    A unique new approach to optimizing EMI decaps (number, location, and type) is profiled in this webcast. The result is a design that is optimized for EMI performance. This flow augments optimization of device specific decaps. The presentation will explain how to get started with these tools and how they speed time to market.

    Watch Now
    Parallel Bus Analysis
    High speed DDRx designs are among the most challenging. This webcast focuses on the complex and interrelated signal integrity issues that have become mainstream concerns. The presentation explains the challenges of parallel bus designs and includes a demonstration of Sigrity's SystemSI - Parallel Bus Analysis.

    Watch Now
    Back Channel Support
    This webcast is presented jointly by Sigrity and Gennum's Snowbush IP Division. Snowbush's IBIS AMI models utilize technology from Sigrity to support back-channel simulation. The presentation will provide an overview of the technology, and explanation of back channel communication, and a demonstration of the tools.

    Watch Now
    Multi-gigabit Serial Link Analysis
    This webcast focuses on an approach to IC package assessment that was pioneered by Sigrity. This approach pinpoints potential design weaknesses early on when fixes are easiest to make.  This offers insight beyond what is typically gleaned from IC package models alone.

    Watch Now
    Integrated Package Layout and Electrical Assessment
    In this webcast a comprehensive approach to multi-gigabit serial link analysis is explained and demonstrated.  This new method enables SI engineers to address issues early and throughout the design process. The presentation will cover requirement for serial link SI analysis, the Sigrity analysis flow, power noise effects on serial links, and more.

    Watch Now
    Cadence Sigrity PowerDC allows the users to predict the correct DC voltage drop based on the operating temperature of that region of the electronic product's printed circuit board. This demo will show you how to use PowerDC to do multi-board electrical and thermal co-simulation.
    See why Sigrity provides the industries leading SI, PI, and Power-Aware signal integrity solutions on the market today.
    DataSheet (PDF)
    Learn how to perform fast and accurate sign-off quality DC analysis with the industry leading Sigrity PowerDC.
    DataSheet (PDF)
    This paper assesses how modern tools can be used to address power-aware SI challenges associated with I/O modeling, interconnect modeling, simulation, and analysis
    Application Note
    Cadence® Sigrity™ SystemSI™ signal integrity (SI) solutions provide a comprehensive and flexible SI analysis environment for accurately assessing high-speed, chip-to-chip system designs covering both serial and parallel interface anlaysis.
    DataSheet (PDF)
    Learn how Sigrity makes it easy to quickly run Impedance and coupling checks on your design to identify areas of concern. No models needed!
    Contact EMA