EDABuilder 3.0

TimingDesigner 9.4

Complete Graphical Static Timing Analysis Environment

  • Graphical user interface allows for easy and context aware definition of critical timing paths
  • Tight integration with FPGA, PCB, and IC design flows enable fast and accurate data sharing
  • Powerful documentation capabilities keeps everyone on the same page with ease
Achieving Reliable DDRx signoff is a significant challenge for our customers. By collaborating with EMA, we are able to provide this unique DDRx timing solution leveraging the unparalleled accuracy of power-aware simulation from the Sigrity solution with the advanced visualization and static timing analysis capabilities of TimingDesigner
Vinod Kariat
VP of R&D for Simulation Products
Cadence Design Systems

DDR Memory

New DDRx Timing Signoff Flow with Cadence Allegro Sigrity

Cadence and EMA have collaborated to provide a unique power-aware DDR timing sign-off flow for complete cycle-accurate system level simulation and analysis. This new flow enables:
  • Comprehensive power-aware simulation of the entire DDR interface
  • Automatic conversion of simulation data into graphic timing diagrams for effective and accurate analysis of results
  • Quickly timing errors and test what-if scenarios in a graphical static timing analysis environment
  • Generate signoff quality documentation and reporting as a byproduct of the simulation & analysis process
See the new DDR timing signoff flow in action for yourself.View Webinar

Enhanced Documentation Generation

The ability to effectively communicate design intent (internally and to customers) is an essential piece of the product development process. TimingDesigner 9.4 provides a full set of tools to generate product documentation directly from your timing analysis projects:
  • Extensive support for annotations and styling to ensure effective communication and adherence to corporate style requirements
  • Support for multiple image export formats
    (JPG, PNG, TIFF, MIF, PDF, and more)
  • Configure exports in live preview window to ensure
    ‘what you see is what you get’
TD Image Export
Verified Parts

Advanced Requirements Analysis

Release 9.4 has added the ability to define guard band or warning conditions to standard pass fail constraint evaluation. Users are now able to not only see when a requirement is pass/fail they can also get visual cues as to when requirements are getting close to failure allowing them to:
  • Identify critical paths early in the design process before a failure is registered
  • Specify extra safety margin above and beyond the manufacturer requirements
  • Determine timing relationships that could benefit from optimization
The timings right. Evaluate TimingDesigner 9.4 today.Free 15 Day Trial

Modern User Interface Improvements

The TimingDesigner user interface continues to evolve in order to take advantage of modern UI paradigms. TimingDesigner 9.4 has enhanced the timing violations and timing calculations viewers with the ability to dock these views right inside the timing diagram window. This enables the designer to have a quick view of the status for all constraints in the diagram without having to leave the diagram window. Users can easily select and filter their constraints to identify violations and then trace the delay paths to explore alternatives.
CAD Exports
These are Just Some of the Features in TimingDesigner 9.4.
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