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Overview Features Multimedia Aldec® Active-HDL™ is a comprehensive design, simulation, and verification environment with all the capabilities necessary to help designers successfully develop and validate their FPGAs. FPGAs are everywhere in electronic design due to their flexibility and time to market advantages. With these advantages comes the challenge of designing, validating, and implementing the increasingly complex logic for these programmable devices. Designers using Active-HDL have a streamlined FPGA design environment that reduces simulation and verification time all at a price that fits in their budget. Active-HDL's high performance, mixed-language Baseline RTL Simulator operates at twice the speed of FPGA vendor simulators. As your design requirements increase Aldec's scalable solutions allow you to increase simulation speed to keep pace with the rise in complexity. Advanced options are also available to further optimize simulation run times and provide metrics on code coverage. Benefits: •    High performance, mixed-language RTL Simulator •    Support for: VHDL, Verilog, System Verilog, SystemC •    Multiple design entry options •    Integrates seamlessly with FPGA vendor tools •    Scalable solution to support you as your verification requirements grow •    Assertion support •    Automatic testbench generation •    Advanced debugging and code coverage •    Import/export legacy designs •    Wide selection of export options, including HTML and PDF •    Supported on Microsoft® Windows® 2000, 2003, XP, and Windows Vista® operating systems Aldec® Active-HDL™ is a comprehensive design, simulation, and verification environment with all the capabilities necessary to help designers successfully develop and validate their FPGAs. High performance, mixed-language RTL Simulator Active-HDL included a high performance, common-kernel, mixed-language simulator supporting batch mode simulation,... High performance, mixed-language RTL Simulator Active-HDL included a high performance, common-kernel, mixed-language simulator supporting batch mode simulation,... VCD, a performance profiler, memory viewer, encrypted IP and FPGA vendor libraries. Drive your system-level simulation model using complex test benches or create quick and flexible stimulator farms to rapidly test design modules and system level designs. Graphic Design Entry Draw any finite state machine diagram and let Active-HDL generate your synthesizable RTL code. Graphic Design Entry Draw any finite state machine diagram and let Active-HDL generate your synthesizable RTL code. Connect all design modules at the top-level and automatically generate output structural HDL using the built-in block diagram editor. If needed, convert HDL to graphics with Code2Graphis utility. Active-HDL can also import, re-target, enhance, simulate, and debug your legacy designs. Support for Many Common Languages Active-HDL provides full support of the IEEE 1076-1993 Standard, IEEE 1076™-2002 VHDL standard, and the majority... Support for Many Common Languages Active-HDL provides full support of the IEEE 1076-1993 Standard, IEEE 1076™-2002 VHDL standard, and the majority... of the recently published IEEE 1076™-2008 Standard. It also has full support for VHDL, Verilog, SystemVerilog (design subset, assertions, or full language), SystemC, and EDIF.  Special settings allow users to select any version of these standards and enable compatibility with older versions. Revision Control Interface Revision Control Interface allows operation on subsequent versions of a design and revisions of design source files... Revision Control Interface Revision Control Interface allows operation on subsequent versions of a design and revisions of design source files... directly from the Active-HDL environment. In addition, design teams can track changes made to a design, view differences between multiple versions of source files, and recover previous file versions at any time. Project Management Tools Active-HDL's extensive project management tools help you track your design progress and interface with FPGA vendor tools... Project Management Tools Active-HDL's extensive project management tools help you track your design progress and interface with FPGA vendor tools,... allowing the user to design through a single user interface. The multi-vendor FPGA Design Flow Manager controls simulation, synthesis, and implementation for industry leading FPGA devices, such as Actel™, Altera®, Lattice®, Quicklogic®, Xilinx®, and over 87 other popular EDA tools. Select Category All ECAD MCAD Select Design Solution All PCB Design Entry PCB Layout and Routing Simulation and Analysis FPGA Development Data Management LifeCycle Management Documentation PCB Design Suites Select Product All Aldec Active HDL FPGA System Planner TimingDesigner Select Content Type All DataSheet (PDF) Application Note Video Customer Success Story Recorded Webinar Sample Files (ZIP) Description Type Aldec Active HDL - Overview Learn how Aldec Active HDL helps designers successfully develop and implement FPGAs in this short video. Video Aldec Active HDL - Webinar A webinar about Aldec Active HDL, a high performance, mixed-language Baseline RTL Simulator. The webinar includes an explanation of the tools capabilities and benefits, followed by demonstrations. Recorded Webinar Aldec Active HDL Datasheet Active-HDL is an integrated FPGA Design and Simulation solution, with design entry, a high-performance mixed-language simulator and an easy-to-use, multi-vendor FPGA flow manager. DataSheet (PDF)

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