Application Note

Modern designs often operate at sub-nanosecond edge rates. At such speeds, it becomes important to resolve timing issues early in the design cycle. When coupled with the need to reduce time-to-market, solving high-speed issues requires early identification, analysis, and specification in the schematic design itself.

Typically, constraint parameters are entered manually in the PCB design phase, which can be tedious as well as misleading. To avoid such pitfalls, the recommended procedure is to populate the constraints at the schematic level before sending it to the PCB designers. This ensures that the constraints are managed by

schematic engineers and reduces the error introduced due to misinterpretations.

This application note discusses the enhanced features that are now available in Allegro^® Design Entry CIS to process different types of electrical constraints and take them to Allegro PCB Editor with a complete front-to-back flow. READ MORE ►

SAN DIEGO, CA

By Steve Sandler and Charles Hymowitz, AEi Systems

This application note discusses the Texas Instruments UC1846 Current Mode PWM Controller, MOSFET gate drive circuit simulations, and voltage doubling circuits. A full transient model for the UC1846 is included in the Power IC Model Library for PSpice^®; for more information please visit http://www.ema-eda.com/products/other/powericlib.aspx.

The circuits in this application note were generated in both breadboard form and in PSpice. The laboratory bench results are compared to the PSpice results. READ MORE ►

• OrCAD Capture: Can a schematic project be treated as a library part that can be instantiated into a new project?

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