Top

Allegro PCB Platform Release History

Cutting-Edge Technology Requires Constant Innovation

Cadence Allegro is a driving force in the PCB design industry and is constantly evolving to meet the demands of today’s technology. Cadence has been accelerating the rate of innovation and delivering a stream of updates and product enhancements to users so designers can easily keep up with the constant pace of change. The release history below provides insight into industry-first capabilities such as advanced layout and routing, intelligent design for manufacturing, chip on board, tabbed routing, intuitive high-speed design, dynamic collaboration, and more.

Version Notes:

  • Cadence provides bi-weekly updates to its products to fix issues and defects as quickly as possible for customers
  • New functionality is also delivered through quarterly incremental releases (QIRs).
  • Customers are encouraged to stay on the latest update within a release as they will not only get access to any fixes but will also have access to new features (as described below) available through the QIR stream.
Related Links

Release History:

Version 23.1

Products Covered: Allegro X Layout Editors | System Capture | Pulse

Allegro X Release. Innovative design platform focusing on providing a cohesive and comprehensive solution for all design requirements.

Allegro X Layout Editors

23.1

  • Enhanced Documentation. Cadence Doc Assistant presents help content as individual easy-to-read topics and has improved the speed and relevance of search capabilities.
  • Counterbore/Countersink. Define secondary drill definitions on either the primary or secondary side.
  • Microvia Slot. Expanded the capability of microvia drill support beyond circle and square-plated holes to include microvia slot. This allows rectangular or oval-plated slots while following standard microvia constraints in the design.
  • Drilled Hole Padstack Definitions. Drilled hole fields for circle and square holes as well as round slot fields for rectangle and oval shot holes have been added for accurate unit-controlled values of the drill hole size before plating and tolerances.
  • Multi-Drill. Pitch values for rows and columns can now be defined to calculate the spacing automatically for a multi-drill.
  • Freeze/Unfreeze Dynamic Shapes. When dynamic shapes need to remain constant to protect critically circuitry and maintain design intent, suspend or freeze dynamic voiding instead of converting to static shapes. Once frozen, new objects entering a shape will not void and will generate a DRC error.
  • Zone Adherence for Symbol Pins. Components placed in a zone with some of the pins protruding into another zone can cause buried or floating pins. Easily check to verify that all pin pads of a component exist on the same placement layer.
  • Nested Zone Support. Designate stackup differences in particular areas of your rigid-flex designs by defining one zone inside another for scenarios where one shape needs to be surrounded by another.
  • Updated Zone Boundary Editing. Zone modifications can now be performed without activating Shape Edit Application Mode.
  • Fill-In Materials. Define the fill-in material for multi-layer PCBs to account for the different dielectric constants that affect the electrical characteristics of conductors running across the dielectric​.
  • Design Review and Markup. Facilitate a collaborative design review environment with the ability to markup and comment design feedback directly in the PCB canvas. Markups are stored in the design database, streamlining the design review process. 
  • 3D Model Mapper. Automatic mapping and fine-tuning of the x, y, and z placement provides efficient methods for mapping 3D models to the footprint directly in the library.
  • 3D Model Export Support. Export the complete 3D representation of the entire design or individual objects as STEP, IGES, ACIS or a PDF.
  • Updated Dimension Line Width. Define dimension parameters to apply a line width globally for all dimensions.
  • Z-Copy Enhancements. Define the net during Z-copy to copy etch shapes to other layers. Incorporate a subclass wildcard to copy the shape to multiple layers.
  • Place Replicate Enhancements. A new delete option will remove routing from the previous module for components that are part of another module.
  • Netlist Import Enhancements. Reuse device files and component definitions that are currently in the design when loading an updated netlist.
  • Net Short Report. New net short properties report is available to easily find all the objects in the design with the Net short property to verify the nets being shorted.
  • Creepage and Clearance Checking. New high-voltage constraint checks to verify creepage and clearance rules. Design Rule check system recognizes non-plated slots between two high-voltage objects and recalculates creepage and clearance. Creepage and clearance vision provides graphical feedback with color-coding directly on the canvas for efficient analysis.
  • Power Delivery Generation. Quickly generate power planes for a section of the design of the entire design based on pin placement, boundary, or design outline. Review power plane escape and adjust placement or constraints to improve power connections.
  • Signal Integrity Optimization in CPU Pin-Field. A new routing tab utilizing complex shapes that follow serpentine pattern contouring to pins and vias allows you to maximize tab size and reduce impedance when routing through CPU pin-fields.

OrCAD X Capture CIS

23.1

  • Enhanced Help Documentation. Cadence Doc Assistant presents help content as individual easy-to-read topics and has improved the speed and relevance of search capabilities. New documentation has been provided for library and part management, part authoring, and more.
  • Enhanced Component Explorer. Access all the library sources along with complete part details in a unified view. The intuitive user interface provides access to various libraries supplied by Cadence, PSpice libraries and models, and external providers.
  • Integration with Content Providers. A new content provider has been integrated into the unified CIS environment. In addition to Ultra Librarian and SamacSys, SnapEDA can now be accessed directly through the schematic.
  • Integrated Part Authoring. Create new components from scratch using available libraries or existing parts from content providers. An easy-to-use dialog box lets you easily configure a description, category, logical symbol, footprint information, PSpice models, and electrical specifications. Incorporate lifecycle tatus, manufacturing part numbers, and more.
  • Part Template Creation. Quickly create parts from templates containing verified symbols, footprints, models and properties and organize the parts in the workspace efficiently.
  • Teams and Workspace Support.  OrCAD X provides a new collaborative development environment to create shared workspaces containing work-in-progress components, projects, libraries, and design files. Create multiple workspaces for different projects and user needs. Share workspaces, define user access and roles to efficiently collaborate with team members.
  • LiveBOM. LiveBOM is a dynamic bill of materials (BOM) that is generated using up-to-date supply chain data with zero configuration. The rich UI provides live part status from cloud libraries including real-time component availability, price data, alternative parts, life cycle status, dynamic part information and more.

System Capture

23.1

  • Thermal Analysis and Celsius Integration. Generate a thermal floorplan to estimate the life of the PCB design and improve placement of components early in the design cycle.
  • Topology Workbench Integration. Launch Topology Workbench directly from the System Capture canvas to analyze the signal integrity of high-speed nets at the schematic, floorplan, and layout stages.
  • Mean Time Between Failures (MTBF) Analysis. Perform MTBF analysis on a design to estimate the performance and safety of electrical, mechanical, and electro-mechanical parts for Allegro X Designer and above.
  • Power Topology Analysis. Enable the verification of all the components in a design in the early stages. Set up a power distribution network on the schematic to estimate the DC power consumption by components in the PCB design for Allegro X Designer and above.
  • Adding Parts to Libraries. In addition to adding parts from external content providers directly into a design, Unified search now supports adding parts to libraries from SamacSys or Ultra Librarian.
  • Library Authoring Enhancements. Create a new template library, create categories and subcategories in libraries to improve component searching, edit multiple parts in a spreadsheet and enhanced part validation improves the library authoring experience.
  • Integration with AWR. Integration to AWR Microwave Office and Allegro PCB Design applications provide a way to create complex PCBs with RF design. Enhancements to this integration include a single impot from AWR Microwave Office into System Capture and more.
  • Variant Editor Enhancements. May enhancements have been added to efficiently complete variant designs including creating function groups, defining alternate parts, defining variants, and the ability to switch to variant views.
  • PDF/A Support. System Capture now offers long-term archiving ability with the PDF/A format in addition to the PDF and SmartPDF formats.

Pulse

23.1

  • Bi-Directional Synchronization with Allegro X EDM and PTC Windchill. Allegro X EDM library parts can be updated with changes in the Windchill part data and vice versa.
  • Dashboard Enhancements. Enhancements to the Pulse Web Dashboard are available to single-user and multi-user environments of System Capture. Enhancements include additional filters, save column visibility, project-specific URL for bookmarking, and more.
  • Version Control. Easily compare two versions of a design to determine the correct path forward as a team. Compare the latest revision or the previously committed version of the design.
  • Offline mode. Users in a multi-user environment can disconnect from the Allegro Pulse server and work in the offline mode, ensuring uninterrupted work using parts in the design cache.

Version History

Version 22.1

Products Covered: Allegro Layout Editors | System Capture | Pulse

Allegro Layout Editors

22.1

  • Topology Editor. A non-analysis version of Topology Workbench for constraint capture is now included. 
  • On-Canvas Structure Update and Variant Creation. When reusing structures multiple times, easily update one instance and push the changes to all instances. 
  • Converting Shapes, Vias, and Pins. Easily convert objects and create or replace an object with a padstack directly on the canvas. 
  • Dimensioning Update. Easily make changes to a dimension without having to delete and regenerate it. 
  • Route Keepout Exception. Easily locate stacked vias and flag them with DRC markers in restricted areas. 
  • Performance Enhancements. Enhancements include better performance on designs with a large number of DRCs, faster update to smooth, better move performance, better performance for shape parameter per layer override, capping of command window messages, and faster DRC checking on designs with negative layers. 
  • Expanded GPU Support. GPU support now includes modern discrete or integrated GPUs from Intel and AMD. Enhancements to NVIDIA GPUs include performance gain in panning and zooming and augmented quality of display. 
  • Normalized Forms for High Resolution Displays. Easily specify a scaling factor to normalize forms that are partially cut off due to display scaling in devices with 4k or higher resolution. 
  • Parameterized High-Speed Structures. Faster structure creation for parameterized high-speed structures by leveraging information from other areas and extracting information from selected differential pair transitions (High-Speed Option Only). 
  • Differential Pair Vias Replaced by Structures. Replace via with structure has been updated to accept structures that do not contain pad entry or exit traces maintaining current routing and delay matching (High-Speed Option Only).

System Capture

22.1

  • Performance Enhancements. Performance and response time has been improved for opening and saving designs, wiring, and canvas selection. 
  • Displaying Base Net Indicators. Configure System Capture to show the winning or base net on the canvas when multiple nets are aliased. 
  • Prefix and Suffix Extended to Physical Net Names. Specify a prefix or suffix for blocks in hierarchical designs. This suffix or prefix is automatically applied to the physical net names for nets and buses. 
  • Block Printing Support. Blocks and pages can be excluded from printing. 
  • Support for Properties on Page Borders. Page border symbols and properties on page borders are now brought in as properties when designs are migrated from DE-HDL. 
  • Open Projects as Read Only.  To avoid accidental editing of designs, especially in a team design environment, lock a design block or page to enable a read-only status and watermark. 
  • Finding and Replacing Special Symbols. Find and replace feature is now enhanced to replace special symbols such as power, ground, or ports. 
  • Controlling Signal Name Copy and Assignment. Define the default behavior for wire name assignment and display settings when wires are connected to a power source or copying circuitry. 
  • Reference Designator Preservation. For multi-section instances or split instances, all sections are processed in a single transaction, enabling reference designator preservation. 
  • Automatic Purging of Bus Bits. In hierarchical blogs where the number of bits were reduced, automatically purge the deleted bus bits. 
  • Connector Pin Assignment. Select a group of components on the schematic canvas and assign pin numbers based on data from the part definition when working with single-pin multi-selection components. 
  • Programmable Parts in Variants. Specify a part code and add a preferred part regardless of the availability of parts in project libraries. Add this preferred part for any variant using a placeholder part number or browse though available parts to choose one. 
  • Visual Cues for DNI Components. Do Not Install (DNI) components in the base design can be indicated with a cross over the component. 
  • Port/Pin Assignment Color Coding. Quickly identify the nets that are perfect matches or partial matches in the Port/Pin Assignment dialog box with color coding. 
  • Printing System-Level Designs. Print system -level designs in all print formats including PDF and Smart PDF. 
  • .MCM File Support. Link the .MCM files from ADP Plus and Allegro System Capture schematic to ensure your project stays in sync. 
  • Library Authoring Enhancements. Edit Allegro DE-HDL libraries directly within System Capture and launch OrCAD Libraries to create or edit OLB schematic libraries. 
  • New Audit Rules in Design Integrity. Improve design creation and quality with additional rules including connectivity checks for MISO and MOSI pins, ref des visibility checks, fiducial checks, test pad checks, and more. 
  • Customization using TCL and Directives. Updated Tcl commands and new directives to improve customization.

Pulse

22.1

  • Pulse as a Layout Source. Define a single source for a layout design within pulse to generate all outputs to Publish for Manufacturing.

Version History

Version 17.4

Products Covered: Allegro Layout Editors | Capture | Allegro Design Entry HDL

Allegro Layout Editors

QIR 3

  • Dynamic Shape Performance Enhancements. Fast mode for dynamic shapes has been improved and significantly improves dynamic shape performance. 
  • GPU Acceleration Rendering. Leverage GPU in Allegro Layout Editors to improve response time during panning and zooming, toggling layers, and render quality. 
  • DesignTrue DFM Enhancements. Improvements include DFF Mask Rule Additions (via and SMD pad overlapping soldermasks), updated calculations for aspect ratio and line-based checks for fillets. DFM Wizard Enhancements to support DFF and DFA templates for copper features, copper spacing, DFA spacing, and component leads. Navigation improvements for the DRC Browser and the ability to waive DRC by group select. Component Lead geometry can now be displayed with control in the visibility pane. 
  • Return Path DRC. Updated to include shape void and plane edge checks to verify trace coverage by identifying overhang conditions and ensuring appropriate plane overlap is present. 
  • Parameterized High-Speed Structures. Easily enter parameters by selecting differential pair vias on the canvas to build a replacement structure for pre-existing routing. Includes five pre-defined geometries: rings, owl, oval, rectangle, and goggles. 
  • Symphony Team Design. Improvements have been made to via structure support, in-session component placement usability and database sharing usability. 
  • 3D Canvas Updates. Isometric view has been added for the bottom side of the board. Other updates include realistic plating thickness, increased model realism, and secondary model support. 
  • Reuse Module Enhancement. Dynamic shapes are automatically converted to static shapes to ensure consistent voiding. Modules applied to the design remain locked to avoid accidental modification. Addition of copper planes, constraint regions and text notes within the module file. Quickly swap a placed reuse module with a different variant in one or multiple locations. 
  • Miscellaneous Enhancements. Multi-pin scribble support when routing, align vias horizontally or vertically to improve routing and plane coverage.

QIR 2

  • Dynamic Shape Enhancements. A new dialog provides a quick way to define layer specific shape parameters. Enhanced performance for dynamic shapes with dynamic fill mode “fast” providing a fast-incremental update to dynamic shapes during interactive operations (Slide, Add Connect, discrete Moves, etc.). 
  • 3D Canvas Updates. 3D mapper now a part of 3D canvas, replacing Allegro (2D) menu. Simplified use model and GUI enhancements. Improved accuracy of collision detection and distance measurements. Additional support for mapping native CAD models (Parasolid, Siemens NX, CREO, SOLIDWORKS). 
  • DesignTrue DFM Enhancements. DesignTrue DFM Enhancements including Enable/Disable Switch for on-line DFM checks, Global Manufacturing Tolerance and Tented Via List Enhancements(top tented via list and Bottom via list). DesignTrue DFM Rule Aggregator combines DFM rules and produces a set of rules with the common denominator based on the most conservative values. 
  • EDMD (IDX) 4.0 Support. Bend sequence ordering, Geometry use identification, primary pin identification, and time stamps. 
  • IPC-2581 Revision C Support. Additional support for rigid flex (bend detail and stack-up profiles), Countersink/counterbore, square drill features, net shorts, and impedance specifications and nets. 
  • Allegro PCB Symphony Team Design. Now Symphony clients can place components directly from the placement list onto the canvas transferring the symbol data to the Symphony server database with In-session component placement. 
  • Allegro Constraint Compiler. Enhancements include improved usability and import of CSV Constraint Tables and XML Constraint Data Set. 
  • Parameterized High-Speed Structures. This prototype solution generates high-speed structures based on parameters. 
  • True Wafer-Level Chip Scale Package Design Support. The Cadence® Allegro® Package Designer Plus Silicon Layout option works with Cadence Physical Verification System (PVS) to deliver flexible silicon substrate and advanced wafer-level packaging (WLP) design capabilities. It offers process development kit (PDK)-driven design rule checking (DRC), density modification and assessment, connectivity verification, and mask artwork signoff. Therefore, the solution is suitable for designs based on emerging silicon and wafer-based packaging methodologies. 
  • Push Connectivity. Now, use the Logic – Push Connectivity (push connectivity) command to push the net of selected pins to all physically connected objects. 
  • Identifying Same-Layer Shorts and Step Coverage Problems Using Serpentine and Comb Structures. Now perform packaging test structure checks for physical opens and shorts in pattern by creating a Serpentine and Comb structure from a set of given parameters.

QIR 1

  • In-Design Analysis: New Flow and Enhancements. Allegro® In-Design Analysis environment blends the best of Allegro® and Sigrity™ technologies to provide analysis and checking capability entirely within the PCB Editor framework for Impedance, Coupling, Crosstalk, Reflection, Return Path and IR Drop. PowerTree files are no longer needed for IR Drop analysis with the ability to define VRM’s directly within the design workflow. 
  • Allegro Constraint Compiler. Support for new types of constraints such as a new table to define Routing Sections within a net or XNet for assignment of Physical, Spacing, and Electrical constraints in an ObjectRule Table. 
  • Allegro Data Management (Version on Commit). Version control features are available as an unsupported prototype within Allegro® PCB Editor and Allegro® Package Designer Plus. Native version control allows you to capture versioned snapshots of a design throughout the design process and provides an easy way for you to reference or revert to a previous version of the design. 
  • 3D Canvas Update. Filter dialog upon 3D Canvas activation to select what layers to visualize in 3D Canvas. Net information (names, type, properties, and so on) is imported into 3D Canvas and the new Nets pane allows you to control how to visualize the nets in 3D Canvas. Dim and Vanish highlighting modes for component selection. 
  • Allegro ECAD-MCAD Library Creator Update. Package Templates have been re-organized for easier selection, Rule Editing has been simplified, and manual footprint creation has been expanded with improved Boolean operations involving path and area geometries. 
  • DesignTrue DFM: New Stack Microvia over Core Via Rules. The new rules manage the number of microvias stacked over a core via, and alignment tolerance from center-to-center of microvia to core via and microvia to microvia. These checks help avoid microvia barrel cracking and via delamination during the entire fabrication process. 
  • Miscellaneous Updates. Custom Icon support for toolbars allows users to add user-selected icons to commands when customizing toolbars. In the Find by Query dialog, a new attribute Width has been added for Lines.

17.4

  • 17.2 Database Compatibility Mode. Open a 16.6 or 17.2 database in release 17.4-2019 and work on it without saving it in the new 17.4 database format. 
  • Symphony Team Design Option. Connect to a Symphony session using an Allegro® Physical Viewer Plus product license to review and mark up the design actively being worked on and not a stale copy. 
  • Hierarchical Route and Via Keepouts. Define keepout by layer type and location using the additional Route and Via Keepout subclasses that have been added to Symbol Editor. 
  • Allegro Constraint Compiler. ACC is a mechanism to inject constraints, at the interface level, with automatic translation of design constraints from an external source directly into Constraint Manager. 
  • IPC 2581 Spec Properties. The IPC-2581 format allows the inclusion of descriptive details that may be attached to specific objects, such as assembly instructions and/or fabrication notes typically displayed within a Fabrication or Assembly drawing. 
  • Mask Defined Pin Annular Ring Check. A new Mask Defined Pad check has been added to the Design for Manufacturing Annular Ring checks and the DesignTrue DFM Wizard template file. 
  • Via Array Update. Addition of a singular array command for adding, updating, and deleting many different array types. On screen dynamics provide you control and feedback by letting you dynamically adjust arrays before placing them. 
  • Contour Routing Update. Enhanced Contour behavior is now the default contouring method as well as additional spacing controls and full constraint region support. 
  • Via Structure Update. A single unified Create Structure form combines the previous Standard, High Speed, and L-Comp forms into one easy-to-use form while also adding descriptions, walkthrough guides and graphics. 
  • 3D Canvas Update. Usability improvements including 3D cutting plane updates, mechanical symbol transparency, Symbol Representation Using DFA_Bound Shapes, and unplated holes in footprints. Pastemask can also be accounted for during 3D models placement.

OrCAD Capture

QIR 3

  • Fully Integrated PCB Viewer. Access the PCB viewer directly from OrCAD Capture and cross-probe between schematic and PCB without needing a PCB license. 
  • CIS BOM Variant. Support for hyphens and underscore in BOM Variant names. 
  • Occurrence Part Update. copy-paste occurrence-based parts across the design. Occurrence properties of selected instance are preserved and copied in the new design. 
  • Access to TI Libraries. Access additional Texas Instrument Libraries from OrCAD Capture including 5000 TI-PSpice Models across 100 unique model categories and as many as 4000 test circuits.

QIR 2

  • Design Sync Updates: Dedicated actions for updating schematic and layout individually. 
  • Schematic Print Updates. Increase schematic PDF readability with the ability to set the schematic print theme independent of the canvas theme.

QIR 1

  • New OrCAD Capture Start Page. After installing QIR 1, as you launch OrCAD Capture, you will see a renewed, content-rich, and reorganized Start Page. It has been designed for you to easily access a variety of information and projects. From this page, you can read about OrCAD Capture, go through brief descriptions of the available features, and access quick start guides and video walkthroughs. You can also access help content, product announcements, and industry news. The page provides contact information for your local channel partners or Cadence Customer Support.

17.4 Base Release

  • Simplified Project Creation and Simulation Flow. The 17.4-2019 release introduces the concept of universal projects, which allows you to create a project without having to select a project type. Further, with the new user interface, you can create a project along with the option to enable PSpice simulation. 
  • Streamlined Workspace. OrCAD Capture provides you with a large set of user-friendly tools and features to easily capture your schematic design. With the 17.4-2019 release, the workspace has been enhanced to ensure fast schematic design creation in an optimized manner. Many new improvements have been done in the Capture workspace to ensure greater ease of use and a satisfactory user experience. 
  • Application and Canvas (Schematic Page) Theme. In the 17.4-2019 release, Capture opens in a dark theme by default. A dark theme reduces power usage, improves visibility, and makes it easier for screens to be read. 
  • Well-Organized Toolbars. Toolbars have been reorganized according to function, and the icons in these toolbars are arranged based on their menus. You can toggle individual icons on or off in the toolbar. 
  • Workspace Customization. Panes are now displayed consistently across all OrCAD applications. All resources opened from a project are displayed as horizontal Tabbed Documents in the canvas area. By default, all panes displaying any kind of output are at the bottom of the application. If multiple panes are open in the output window, they are displayed as docked and tabbed panes. 
  • Enhanced Search Pane. The Find command is now available as a separate pane, called the Find pane. It allows you to specify a property value string and lets you select the object that you want to find. Capture then searches for all objects that match the specified string. 
  • Online DRC. The enhanced user interface of Design Rules Check introduces a new option—Online DRC. Set this to On if you want to check and list design rule violations dynamically as you create or update a schematic design. The Design Rules Check window enables you to set the rules to be run in Batch and/or Online mode. 
  • Design Sync. To efficiently and easily synchronize changes from schematic to layout, and from layout to schematic, a new user interface, Design Sync, has been introduced in 17.4-2019.Using the Design Sync window, you can view the differences between a schematic and the layout for a board, and synchronize the layout from schematic or schematic from layout. Designed with the capability for in-memory synchronization, you can use Design Sync to review the type of change, addition, modification, or removal of a design object without saving the design/layout. 
  • Accessing External Parts from Capture. Using the Place – Search Providers menu, you can search for and download millions of electronic components, symbols, footprints, manufacturer datasheets, and 3D STEP models from Cadence-supported content providers — SamacSys and Ultra Librarian (link is external). You can easily find the part you require and place it in your design. The part, its associated metadata, and any available ECAD models, are saved to your local library.

System Capture

QIR 3

  • Simplified Library Mode. Choose a library format when creating a design and library mode is displayed on the status bar. The library mode is locked when connected to a remote pulse server. 
  • Part Manager Enhancements. Updates to part version comparison and property placeholders are now displayed with the symbol graphic. 
  • New Controls for NetGroups and PortGroups. Hover over a netgroup to display all its members in alphabetical order including netgroups, buses, and scalar nets. Automatic creation and renaming netgroups and members. 
  • Session-wide Automatic Cross-probing. System capture can be set to always cross-probe and applies to all tabs across all applications (System Capture, Constraint Manager and PCB Editor). 
  • Layout File Support. Ability to view and create layout files is now included within System Capture. 
  • Usability Enhancements. System capture now supports grid units in mm and inches. Automatic identification of locale and location settings for menus, tool tips, errors messages and notes on the canvas. 
  • Symbol Editor Enhancements. Parts are now organized into categories, configure the default settings for symbols, and expandable/collapsible libraries. 
  • Reliability Analysis Improvements. Option to review device parameters before electrical stress analysis and waive device/audit check from the dashboard. Instead of full design simulation, subcircuit simulation is now available to save time and improve performance. New schematic audit rules added to analyze and improve your designs. 
  • Pulse Platform Integration. Improved integration including assigning permissions for block and pages and update notifications for linked schematic and layout. 
  • Build Complex Queries. Quickly identify parts in the unified search by building complex queries using search facets. 
  • CIS Manufacturing Information. Manufacturer part details are now support in the Unified search when defined in a linked CIS database table. 
  • Miscellaneous Improvements. Version support for special symbols, added source column in violation window, selection mode changes.

QIR 2

  • New Library Solution. Allegro System Capture now comes with a new native library format that also has complete in-tool support for creating libraries and parts. This means that not only can you create logical schematic designs in System Capture, you can now also create and edit libraries and parts 
  • OrCAD Capture Design Import. The direct library access for OrCAD Capture Libraries and CIS DB from System Capture has been enhanced in this release. You can now create System Capture designs that are based on OrCAD Capture designs as well as import OrCAD Capture designs as blocks into a System Capture design. 
  • Design Flow Features. Power and Ground Signals Connect to Vector Pins, Implicit and explicit Power Pins Connections now displayed in the property pin table, Support for splitting large pin-count design and the placement of the split parts is now available. 
  • Reliability Analysis. New enhancements including Assign or Change Device Categories, Custom Model Support, Additional Schematic Audit Checks, Temperature Sweep Support and Dashboard Enhancements for Device Log. 
  • Pulse Platform Integration. Pulse Platform Integration improvements including Team Design Enhancements, Design Project Creation From Templates, Addition of Electrical Parts to the Live BOM, and Local Parts Support in Unified Search. 
  • Usability Enhancements. Improvements to panning, support for 4K displays, links in session logs, navigation, easier selection of objects within shapes, common operations and more.

QIR 1

  • Continued Focus on User Interface Enhancements. Enhanced user experience as designs are created and managed across the PCB ecosystem. Changes to improve the ease of use and accommodate the newly added functionality to the properties window and preferences dialog box. 
  • Access to OrCAD Capture Libraries. Existing OrCAD Capture designers can directly launch System Capture and create a project that uses components from libraries configured for OrCAD Capture. OrCAD Capture Libraries and the CIS database is fully supported. 
  • New Wiring and Connectivity Engine. Changes that make routine wire drawing, moving, resizing, or pasting components or wires much smoother including guided bend points to avoid unintentional jumps and non-orthogonal wire support . 
  • Changes in Design Storage and Impact on Part Manager. The design storage architecture and part manager of System Capture has been enhanced to support the newly introduced concurrent team design feature. 
  • Design for Reliability. Using Design Integrity, you can run a reliability analysis of schematic designs opened in System Capture. Accounting for component variability and generating electrical stress analysis reports, Design Integrity determines circuit performance under a worst-case scenario thus shortening the design cycle. 
  • Pulse Platform Features. Enhancements to the Pulse Platform including Unified Search Supports Library Search, Sharing Designs Across Teams and Live BOM.

17.4 Base Release

  • User Interface Changes. Enhancements to the Project Viewer and Properties Window, Dockable windows, Optimized Toolbar, Special Symbol Preview and changes in Menus Shortcut Keys Behavior for improved usability. 
  • Enhancements for Object Selection and Replacement. Easily find and replace objects in the design with enhanced Selection Filter, and options to Replace Special Symbols and Replace Sheets Across Designs. 
  • Extended Design Reuse Options. Create New Project from DE-HDL and Import Voltage from Constraint Manager. 
  • Reporting Block Differences. A command-line utility is now available that compares logical connectivity between two designs, or two versions of the same design, and generates a list of netlist differences. 
  • Preserve Locally Edited Hierarchical Block Symbols. You can now edit the symbol for a block created by another user after instantiating it in your design hierarchy. 
  • Custom XNet Pin Pairs Definition. A new panel has been added to the Properties tab displaying XNet pin pairs
  • Improved Logging and Crash Handling. Event logging has been enhanced and all log files are stored in Pulse Data Mart. In the case of an unexpected tool exit, a zip file is created that contains diagnostic data. 
  • Pulse Platform Integration. System Capture now comes with embedded data management. Data is controlled internally when the Save command is used or Commit Points, which offers simple branching support, easy rollback and version preview without opening.

Pulse and EDM

QIR 3

  • New Feature for Designers in Enterprise Environments. Enhancements for web participants through project dashboard including access to unified search, project-specific BOMs, schematic version tree with viewable PDF, separated project BOM and Search tabs, and separate web browser tab support. Set component usage standards such as reliability, availability, EoL date, etc. 
  • Enhancements to Pulse Infrastructure. Designs can be automatically shared with users or groups on creation. Automatic logged into Pulse after any VPN connection interruptions due to network problems. 
  • Library Synchronization Service Enhancements. Options have been included for classification and property mapping between a PLM system and the ECAD component database system, library synchronization configuration management using the user interface, and using PTC Windchill with PingFederate. Enhancements in the Publish for Manufacturing Utility and Processing. Option to create or modify multiple templates, template assignment to users/groups, template import/export and the option to save template configurations in the Pulse platform. Link PLM Part Numbers with New Part Request to ensure that the central parts repository is in sync with PLM system.

QIR 2

  • Web-Based Access to Allegro System Capture Designs and Some Pulse Features. To simplify access to Pulse and its features for administrators and non-ECAD users who might not need access to authoring applications such as Allegro System Capture, PCB Editor, or APD+, this release provides you with a Web Participant. 
  • Enhancements to the Pulse Server Infrastructure. Cluster and Node Health Enhancements Distributed Debug Test Case Generation, Assignment of Multiple Roles to Users, Mixed Tier Support, and Unmanaged Library Support in the Pulse Server 
  • Adhoc Team Design for Allegro PCB and Packaging. Support for Allegro PCB Editor and APD+ designs within the Pulse platform. 
  • Auto-uprev of Pulse. When you open a Pulse-aware application, such as System Capture or PCB Editor, Pulse automatically updates its designs to the latest release. 
  • Enhancements in the Publish for Manufacturing Utility and Process. Windchill PTC Part Data Synchronization, BOM Data Sources in Publish for Manufacturing, Publish for Manufacturing Summary Report, and Publish for Manufacturing Completion Notification

QIR 1

  • Data Security with Authentication for Pulse PlatformThis release enables data security with authentication for users to work with the Pulse platform. To easily keep track of the number of users customers register with the Pulse platform, Pulse displays the user slots in the Pulse Manager page, which can be easily accessed via a browser. 
  • Enhancements in Pulse Cluster Manager User Interface. includes the introduction of an overview of the usage of all servers in the cluster, access to a greater number of services, and tooltips for each field. 
  • In-Design Workflows in Multi-User Environment. Centrally-managed, configurable task-oriented workflows, which are version controlled and allow role-based editing. 
  • Part Requests in Multi-User Environment. This release provides an option for designers to submit requests for new parts to librarians or for changes to existing parts. 
  • Enhancements in Publishing ECAD Data for Manufacturing. This release now supports custom variables, variant filtering and comparison, and variant specific attachments when publishing ECAD data to the file system.

17.4 Base Release

  • Pulse Platform. The desktop and server-based data platform of Allegro EDM is implemented in a microservice framework, referred to as Pulse. The framework provides services such as library management, the ability to search for parts, embedded data management, and enterprise PLM integration. 
  • Pulse Manager. A web-based administration console used to configure the Pulse platform. Easily accessed through a browser, Pulse Manager allows you to configure the Allegro EDM server and its clients, manage your logs, data, disk space quota, data backups, and various other tasks. 
  • Release to PLM. Enables users to easily publish design data, including the ECAD BOM and any manufacturing deliverables, to an enterprise’s PLM system or its manufacturing partners. 
  • Support for TLS 1.2 for Client-Server Communication. To continue to secure communication, privacy, and data integrity between the Allegro EDM server and its client servers, this release adds support for the industry-standard Transport Layer Security (TLS) 1.2 cryptographic protocol.

Allegro Design Entry HDL

QIR 2

  • XNets Status on Canvas. You can now show or hide a visual indication on the components with or without XNets.

Version 17.2

Products Covered: Allegro Layout Editors | Capture | Allegro Design Entry HDL

Allegro Layout Editors

QIR 7

  • DesignTrue DFM in OrCAD and Allegro PCB Editor. Design for Fabrication Rule Enhancements, Design for Assembly Rule Enhancements, Design for Testability Rule Enhancements including copper features, pacakge to package spacking, and design for test checks. 
  • DesignTrue DFM in Allegro PCB Editor Venture/Enterprise. Design for Fabrication Rule Enhancements, Design for Assembly Rule Enhancements, Design for Testability Rule Enhancements including micro via aspect ratio, package to package spacing, component lead checks, and design for test checks. 
  • Component Lead Editor in Allegro PCB Editor. Define lead type and physical details, position the lead in the symbol, view the lead contact area graphically, and enable DFM lead checks. 
  • DesignTrue DFM Ecosystem. Request fabrication rules directly from the supplier and receive those rules in the constraint technology file format. You can then directly import the rule files received into Constraint Manager. 
  • Allegro® PCB Symphony Team Design Option. Connect to a common database to perform collaborative design activities. Each team member sees the design updates in real time without generating or importing design partitions. Whether there is a formal project team or an ad hoc team, you can share the current design and invite other designers to join or assist. Symphony Server Manager provides remote management of Symphony server applications on a dedicated hardware server. 
  • Return Path DRC Enhancements. Now includes the ability to define table-based reference layer assignments at the net level. 
  • Sigrity Technology-Driven High-Speed Signal Analysis and Checking Enhancements. Two new Analysis Workflows are now available: Reflection Analysis and IR Drop Analysis. Updates to Licensing Use Model and general enhancements including net support in Return Path Analysis. 
  • Backdrill Enhancements. Ability to disable oversive antipads and keepouts. 
  • Component Group Move with DFA Feedback. DFA feedback in the form of a spacing circle for mulitple components. 
  • 3D Canvas Update. 2D Window Select, Reverse Cutting Plane and transparency control. 
  • Place Vision. Provides Guidance for Xnets rat filtering, timing driven placement and component association. 
  • OrCAD Professional Enhancements. Sigrity Technology Driven High-Speed Signal Analysis and Checking, Vision Manager, Timing Path support for Z-Axis Delay, Pin Delay Property for Extended Timing Path into Packages, Differential Pair Dynamic Phase Control, Backdrill, Net Group Enhancements, UI/UX Analytics, Design Previews, New Board Creator 
  • Miscellaneous Updates. Color Dialog Global Search now considers every class and subclass when searching. Modernized Command Pane is now a productized feature and no longer requires an environment variable

QIR 6

  • Enhancements in Design for Fabrication Rules. Exclude pin or outline to component checks. New Design for Assembly (DFA) Rules including outline, spacing, and pastemask rules. DesignTrue DFM in Allegro PCB Editor Venture Product updates including tented vias, void sliver checks, micro via stagger, outline to pin-pad exclusions, DFA (outline, spacing, pastemask, and fiducials) rules. 
  • Enhancements to Sigrity Technology Driven High-Speed Signal Analysis and Checking. Two New Analysis Workflows are available: crosstalk analysis and return path analysis. Return Path ERC now includes DRC to check for stitch via with radius from center of signal via. 
  • Dynamic Shape Quality and Performance Initiative. Dynamic shape voiding has been improved in this QIR. Abnormalities referred to as spikes or slits in shapes are addressed. This enhancement reduces or eliminates the need to add oversize clearance properties as a workaround. To improve shape voiding performance, a new Fast Mode has been released. 
  • Return Path DRC Enhancements. The Return Path DRC includes a check for stitching vias. 
  • Productivity Enhancements. Quickplace by Schematic Layout, Place Replicate Enhancements, Via Array Update, Route Clearance View, Enhancements in Copy and Paste Commands, Via Structure Update, Basic PDF Export, Show Measure Update, Mechanical Hole Checking, Zones with Placed Symbols 
  • Allegro® PCB Symphony Team Design Option. Symphony Team Design Enhancements including 3D Canvas support, Z-copy support, create bounding shape support and client cursor location and tracking. 
  • Productivity Toolbox Update. Testpoint to testpoint checking, Testpoint to component checks based on height depending spacings, Visualization of restriction areas, DRC marker generation, Constraints reuse through configuration files 
  • RF PCB Enhancement. A new library workflow has been introduced that uses unified RF library to support mixed MWO and ADS components in a layout design.

QIR 5

  • Return Path DRC Updates. The new Return Path DRC Vision option provides return path feedback based on the constraints system. Nets with a return path constraint assigned to them display trace segment color coding that indicates adherence to constraints. You can enable the Electrical Analysis modes for Return Path DRC in the online mode. The online mode keeps RC markers up to date without a Batch DRC update. 
  • DesignTrue DFM. DesignTrue DFM has been enhanced in the Venture license with the addition of backdrill. 
  • Allegro and OrCAD PCB Editor Canvas Enhancements. Improvements to the Start Page, Design Workflow Pane, Frequently-Used Icons, Customizable Design Canvas, Improved Graphic Response Time, and Modernized Command Pane. 
  • Find by Query Update. This command allows viewing of all the objects in the Find by Query dialog. You can query a design database for certain type of objects by filtering them based on associated properties. 
  • Route Vision (Segment Suppression in Pads). A new option to suppress segments that are entirely inside pads. This functionality reduces the report size by suppressing issues that are not present after the etching process. 
  • Timing Vision Update (Static Phase at Vias). Timing Vision has been updated to properly display phase information for the new static phase at via sites rule check. This functionality allows you to add phase rules to individual pin-via pairs. 
  • Productivity Enhancements. Including DFA Update, Assign Net to Via, Via Label Enhancement, Padstack Editor, File Locking, and Temp Group support in Application Modes 
  • Allegro PCB Symphony Team Design Option. Updates include hover over datatip for identifying lock owner, DRC Browser support, Read-only SKILL support, Integrated Design Analysis and Checking, Technology Dependent Footprints, Shape Editing, constraint edit mode, and symphony server. 
  • Common Allegro-Sigrity Material File File Format. A new file format that supports all material information is now available as an option for use in Allegro® and Sigrity™ environments. 
  • Miscellaneous Enhancements. Other enhancements include associated Components Support for Bypass Capacitors and Uvia/BBVia Spacing Support for Via Patterns 
  • IC Packaging-Specific Updates and Behavior Changes. RFPCB option is integrated into SiP Layout.

QIR 4

  • In-Design DFx. In-Design DFx Environment consists of bare-board fabrication checks that are defined as constraint sets in Constraint Manager. Constraint Manager contains a new Manufacturing worksheet. Allegro Venture PCB Designer and In-Design DFx Checks are expanded to address additional DFF checks and analysis that compliment the technology-based features. 
  • DRC Browser Updates. including Windowing into the location of a selected DRC, A tristate status of DRC violations (Read, Unread, Review), Various navigation methods, The ability to assign the waive DRC attribute to a selected DRC, Various filtering and sorting methods, A DRC Chart to see a graphical representation of where to resolve the issue. 
  • MCAD Collaboration Environment. Streamlines the ECAD/MCAD flow for IDX, reducing the concern for managing the multiple changes and modifications that occur during the design cycle. 
  • Sigrity Technology Driven High-Speed Signal Analysis and Checking. A new, unique environment blending the best of Allegro® and Sigrity™ technologies that provides analysis and checking capability entirely within the PCB Editor framework. Updates include Impedance Analysis Workflow, Coupling Analysis Workflow, Impedance DRC Vision, and Graphical Overlays. 
  • Differential Pair DRC Enhancements.  Enhancements have been made to the way Static Phase is calculated. It now includes via transitions when checking back to Driven Pins and specific spacing constraints, to control the minimum spacing between the vias of the members of a differential pair. Updates to Static Phase Control at Via Transitions, Intra-Differential Pair Spacing Rule, and Return Path DRC 
  • Routing Applications. Updates to Route Vision, L-Comp Structures, Route Optimization, Route Clearance View, and Net Short Usability Improvement 
  • Productivity Enhancements. Dynamic Component Alignment, Dynamic Ratsnest Update, Place Replicate Module Locking, Place Replicate-Apply Enhancement, Multi-site Copy/Paste, Create Bounding Shape, and Padstack Editor XML Import/Export. 
  • Allegro PCB Symphony Team Design Option. Updates include Placement Edit Application mode, Place replicate support, component alignment, pin swap support, differential pair phase tune, Impedance vision, Add Line, Arc w/Radius, 3pt Arc, Circle and Text commands Text Edit command, and pause session support. New multi-threaded communication architecture improves performance by dividing server related tasks into multiple threads. 
  • Miscellaneous Enhancements. Updates to Thieving with Hexagon Shapes, Cross Section Chart and Table update, IPC356 Export, New Via Structure Report, New Properties, and New ENV Variables. 
  • Productivity Toolbox Updates. Updates to the Shield Router including new cline shield option is available as an advanced setting. A cline shield must connect at least to one pin/via/shape assigned to a net. Soldermask can be enabled as an advanced setting. Size and gap can be specified in a similar way like etch layers. New gap value for tandem shields where value specifies the size of a user-defined void to be generated in the tandem shield  along the selected cline structure. 
  • Enhancements for Analog/RF Option of PCB Designer and SiP Layout. Enhacements made to Clearance Commands and Via Array Commands to increase productivity. 
  • IC Packaging-Specific Updates and Behavior Changes. Updates to Fillets and the Plating Bar and performance.

QIR 3

  • Allegro® PCB Symphony Team Design Option. You can now perform some additional tasks including component swapping, Move, copy, change, and spin of dynamic and static shapes, and test point generation.  
  • Dynamic Ratsnest. Rat lines are updated dynamically as the component is moved. When the component is moving, a temporary highlight color is used. 
  • Route Keepout Net Exceptions. Create a route keepout exception by net group. You can create a route keepout shape and assign a route keepout (RKO) group to it. 
  • Padstack Editor XML Import.  Import an XML file that contains the full padstack definition to the Allegro Padstack Editor. 
  • Import File Manager. New Import File Manager function in the PCB Editor detects new or updated import files and displays a pop-up notification indicating the file is ready for import. The notification also provides options to start the update process or to be reminded later. 
  • Relative Grid. The Move command now has a new setting Relative Grid in the Option tab. It allows to set the definition of X or Y grid values that are based on either the drawing origin or an alternate relative grid origin. 
  • Multi-Destination Paste. This command copies objects to multiple destinations, and snaps them to the center of selected destination objects.This offers more speed and control when copying objects to multiple locations one at a time using the current Copy command. 
  • Route Clearance View. New routing visual assistant that aids in estimating space available in channels during interactive routing. It can be quickly and easily determined if routing is possible through a channel based on the spacing and width constraints. 
  • Miscellaneous Enhancements in PCB Editor. Updates include Pre-selection Use Model , Inter-Layer DRC Update, and Symbol Editor Update. 
  • RF PCB Enhancements. Now supports placement of via structures, Checks DRCs only when placing via arrays, An option to enable the preview of via array.

QIR 2

  • New Concurrent PCB Team Design Environment. Allegro® PCB Symphony Team Design option allows you to connect to a common database to perform collaborative design activities. In this solution, each team member sees the design updates in real time without generating or importing design partitions. Whether there is a formal project team or an ad hoc team, designers can share their current design and invite other designers to join to assist. 
  • Introducing the New 3D Canvas (Unsupported Prototype). 3D Canvas Navigation, 3D Canvas Controls, Basic Collision Detection, 3D-2D Selection/Highlight, Full Layer Modeling of Mask, Silk, and Dielectric Layers, 2D-3D Interaction, Object or Window Select, File Export. 
  • Interactive Routing Enhancements. Routing with Via Structures are now fully integrated. 
  • Create Flow (Design Planning Option). The Create Flow command lets you draw a guided route path (similar to drawing an etch) and automatically routes the connections. 
  • Route Optimization (Unsupported Prototype). The new routing behavior has been designed to center routes in a channel. 
  • Shape Applications. Updates include Automatic Island Deletion, Island Void Deletion, and Shape Voiding Behavior.
  • DFA Table Support for Embedded Layers. The DFA constraint spreadsheet has been enhanced to support dedicated clearance values for embedded component layers. 
  • Miscellaneous Enhancements. Show element now reports if a via is part of a stack,  if a keepout is part of a pin/via and its pad keepout type, and zone name where pins and vias are located (for rigid-flex designs only). Show measure supports lines and clines. Improved performance by caching stale directories in the PATH variables. Updates to IDX, Symbol Editor, IPC-2581, Derive Connectivity Utility, DBDoctor, and Mirror Geometry.

QIR 1

  • New 3D Canvas (Unsupported Prototype). This release includes a graphics engine upgrade which brings higher quality visualization and speed when panning and zooming. Other features available in the 3D canvas include collision detection, etch layer visibility controls, and cross probing to the 2D canvas. 
  • STEP Model Mapping to Devices. Enhanced to support the mapping of a step model to a device as well as the package symbol. 
  • Bend Editor for Flex Design Applications.  Define a bend line that represents the center of a bend zone arc. The bend line parameters assigns attributes that are attached as a property to the bend line. Once the line is defined, a bend area is created that visually displays the extents of the bend based on the bend values. There is also an option to add via keepout and package keepout geometries relative to the bend area’s outline geometry. 
  • Shape Application Mode Updates. Assigning parameters to multiple dynamic shapes, add Notch Updates, and Slide IX/IY Support. 
  • Find by Query. Easily locate the complete set of design elements in the canvas. 
  • Route Optimization (Unsupported Prototype). Updates to route optimization including Via Structure Update, Group Routing, Create Flow Update (Unsupported Prototype), Bundle Layer Control, Enhanced Bundle Viewing, Tab Routing Update, Add RF Trace, and Convert RF Trace. 
  • Chip on Board (COB). Supports basic wirebond applications. New Subclasses are available to support the package symbol that includes die pins. 
  • Productivity ToolBox Updates. New features have been added including PCB Design Compare and Custom Variables. 
  • RF-PCB Enhancements. Enhancments to Clearance Commands, Via Array Command, and Performance Improvements.

17.2 Base Release

  • Padstack Overhaul. New Padstack Designer User Interface, Padstack Usage Types, New Pad Geometries, New Drill Features, Multi-shape mask pad geometries, User Mask Layers Increased to 32, Keepout Features, Padstack Options, and Summary Report. 
  • Layer support for Dynamic Shape Properties. The thermal and clearance properties associated with Dynamic Shapes can now be applied on a per-layer basis. 
  • Cross Section Overhaul. The Cross Section Editor has been redesigned leveraging the underlying spreadsheet technology found in Constraint Manager. Updates include General Enhancements to Cross Section Editor, Multi-Cross Section Support for Rigid-Flex Design, and Cross Section Support for Non-Conductor Layers. 
  • Rigid-Flex Physical Zone Management. A physical zone is used to map that respective area of the design to one of the stackups created in the Cross Section Editor. Zones can be rigid or flex areas consistent of varying layers. Updates include New Database Classes and Subclasses, Design Uprev, Visibility Pane – Access to Mask Layers and Zones, and Dynamic Zone-based Placement. 
  • Enhanced Contour Routing. A new prototype feature that provides a more efficient method to add routing during Add Connect by following an existing connect line or a route keepin. 
  • Crosshatch Shape Update. Use of dynamic crosshatch shapes is prevalent in flex designs. Crosshatch is lighter in weight and is less prone to cracking when material is flexed. Adding dynamic crosshatch shapes becomes easier in the 17.2 release as the shape fill drop-down menu now supports the dynamic crosshatch entry. 
  • Inter Layer Checks for Rigid-Flex Design. New inter layer check functionality that provides the ability to check geometries between two different class/subclasses. 
  • Manufacturing Prep – Rigid-Flex Design. Supports an option to output a multi stackup table. The table supports entries for all conductor and non-conductor layers, material and thicknesses. 
  • Embedded Component Design Updates. The Copy command now supports embedded package symbols. The Swap Components command can now be used on dummy components. Embedded Soldermask subclasses are now supported (similar to Pastemask). 
  • Backdrill Overhaul. The Backdrill application has undergone some significant enhancements. Backdrill data is now stored in the library padstacks and utilized at the design level during the analysis and backdrill generation process. Padstacks which do not have pre-defined backdrill information can be automatically updated at the design level by the entering the backdrill criteria prior to running backdrill. Design layers which are backdrilled will have Route Keepout Shapes generated to ensure that design integrity is maintained with separate padstack definition controls for the backdrill start layer, internal layer and negative layer anti-pad geometries without the need for custom padstacks or scripts. All backdrill data is available on the individual Pin/Via objects displayed on the canvas or by simply querying the object using Show Element, and generating the Backdrill Legends and detailed Backdrill Report. In addition, the setup time for backdrill can now be improved as a result of algorithms designed to create intelligent layer pairs. 
  • Shape Edit Application Mode. The Shape Edit Application Mode is a tuned editing environment primarily designed to increase efficiency with shape boundary editing. It is available in all backend PCB and Packaging products. This object-action environment simplifies the actions of sliding a shape edge, adding a notch or chamfering/rounding the corners. 
  • High Speed Interconnect Enhancements. Return Path Via support is now extended to support single net routing. 
  • Tabbed Routing. Tabbed routing is a new routing strategy in which trapezoidal shapes called tabs are added to parallel traces to control impedance in the pin field/breakout region, and crosstalk in open field region. This enables longer trace lengths and use of smaller trace spacing. 
  • Via Structures.  Allows you to create two types of via structures – standard and high speed. There is also an option available to automatically export an XML file, which can be used to import/export via structure definition in other PCB/SiP database and Sigrity 3DEM (High Speed only). 
  • Acute Angle Detection. A suite of four angle based checks are introduced in 17.2 as Design Level DRCs. 
  • Drill Hole DRC. A new Spacing Options section is added to the Analysis Modes menu to host a toggle control for this purpose. The option is labeled Check holes within pads. 
  • IDX Enhanced Features. Updates to User Preference Settings, IDX Properties, Component Symbol Support, User Defined Layer and, External Copper Layer Support, and IDX Compare Utility 
  • OrCAD Layout Footprint Libraries Added to PCB Editor Libraries. OrCAD Layout footprints have been translated and integrated with PCB Editor. 
  • Database and Misc Enhancements. Updates include Metal Usage Report, Refresh Symbol – Maintain Padstacks, Performance Improvements, New Variables, New Properties, Modified Properties, Skill Enhancement, Import Logic Enhancement, Design Length Enhancement,  and Material Name Length Enhancement. 
  • Productivity Enhancements. Updates to Backdrilling, Differential Pair Dynamic Phase Control, Highlight Segments Over Voids, Spread, Lines between Voids, Via-Via Line Fattening, and Contour Routing. 
  • RF PCB Enhancements. Enhancements to RF Status Display, Clearance Initialization, and Cross-probing between Schematic and Layout

OrCAD Capture

QIR 7

  • Enhancements in Part Editor. With QIR 7, you will see the following enhancements in part editor:
    • In-place editing of text objects
    • Enhanced Edit pins dialog box
    • View package information
    • Additional grid control
  • Integration of Constraint Manager with OrCAD Capture. Constraint Manager is a cross-platform, spreadsheet-based application used to manage constraints across all tools in the Cadence® PCB and IC Package design flow. With this hotfix, Constraint Manager is integrated with OrCAD® Capture.

QIR 5

  • Simplified Interface for Associating a PSpice Model. You can now accomplish the following tasks to associate a PSpice model using a simplified user interface:
  1. Select a PSpice model library
  2. Display and select the mathcing models
  3. View model text and symbol graphics
  4. Perform pin-port mapping
  • Launching Footprint Viewer from Capture. In this release, Capture enables you to view the footprint associated with a part. The footprint viewer provides a two-dimensional view of the footprint symbol of the part selected on the schematic. Along with the footprint symbol, the viewer also shows the pin numbers and pin names. 
  • New and Simplified Part Editor. you will see a new version of the part editor. A new user interface has been introduced where you can view and modify all properties in a single integrated pane, called Property Sheet.

QIR 4

  • Performance Improvement.: Performance has been improved for various design specific cases, such as designs with large number of netgroups.

QIR 1

  • Design View in HTM. This new feature allows you to export a complete schematic design as a single HTML file, and view the design in the specified internet browser (Google Chrome recommended). 
  • Saving Design Differences to HTML or Excel. OrCAD® Capture Design Differences Viewer now supports the ability to save the design differences into HTML files (.html) or Excel files (.xls). 
  • Passport Protection to a Design in Capture. You can now add a password to a design, remove an existing password applied to a design, or modify an existing password applied to a design. 
  • Configuring Properties. You can configure the Find window properties and Browse Parts window properties using the Configure Properties window. 
  • New Utilities. New utilities have been added in OrCAD Capture to automate some of the manual tasks, including: Communication Server, Replace Path in Design Cache, Show All Open Libraries and Design, Customize Page, Check/Correct Corrupt Library, and Find and Replace Text. 
  • Display Checkbox in Add New Property Dialog. Enable display of user-defined properties so that you can set display properties while creating a new user-defined property. 
  • Updated Property Editor Filter in the Properties Editor Window. Updated and flow-wise property spreadsheet filters are now available, so you don’t need to search for commonly used properties for a flow. 
  • Global DRC Settings for Global Environment. A new option, Use Global DRC Settings, has been added in the DRC tab of the Extended Preferences Setup window. By enabling this option, you can use the same DRC settings globally for various different designs to enable standardization of a DRC setting across projects, sites, and teams

17.2 Release

  • Design Difference Viewer. New feature to perform logical and graphical comparisons between two designs, two schematic folders or two schematic pages and view the difference report in the form of a portable HTML format. (Watch Demo Video) 
  • Advanced Annotation. The new advanced annotation feature lets you annotate multiple schematic pages at a time giving them complete control over their component annotation process in the design cycle. (Watch Demo Video) 
  • Open Demo Design. The new Open Demo Design browser gives access to more than 150 demo designs made available from different locations, collated together to help users better understand Capture, Capture CIS and Capture _ PSpice Flow. 
  • Export – Import XML. OrCAD Capture provides you the capability to convert Capture designs to XML format and vise-versa based on the requirement. 
  • ISCF Export. Introducing direct ISCF (Intel Schematic Connectivity Format) feature for automating Intel-based design reviews to export hierarchical schematic designs in an Intel-approved format helping you optimize the design review process. 
  • PDF Export. The new PDF export functionality lets you export Capture design as PDF file and provides intelligent design information. 
  • Extended Preferences setup. The extended Preferences Setup window allows you to modify additional application settings in OrCAD Catpure like Command Shell, design and libraries, design rule check, CIS, NetGroup, NetList and Schematic.

Allegro Design Entry HDL

QIR 6

  • Enhancements in Design Entry HDL. Replace parts with specific parts, Generate Netlist in ISCF. 
  • Enhancements in Variant Editor. Compatible footprint check, customized variant BOM generator, change properties for multiple components.

QIR 4

  • Support for Data Tips. Provide part-specific recommendations and guidelines as datatips to designers for quality purposes. 
  • Ability to Lock Components. DE-HDL now allows you to identify a component as locked so as not to allow any changes. 
  • Support for Block Re-import. DEHDL now supports the re-import of read-only blocks. The location from where the source block was imported is stored, and checked periodically for changes. DE-HDL informs the user if the source changes. 
  • Moving Off-grid Components to Grid. Move off-grid components to the grid when reusing schematics to ensure successful wiring.

17.2

  • Enhancements in Allegro Design Publisher. Watermark support in PDF creation and PDF/A Support. 
  • Constraint Manager Database Changes. File type changed for better performance.

Version 16.6

Products Covered: Allegro Layout Editors | Capture | Allegro Design Entry HDL

Allegro Layout Editors

QIR 7

  • Route Interconnect Optimization. Scribble Mode Routing is a simple routing mode that allows you to scribble a route path onto the canvas. The new Auto-Interactive command is designed to generate the interconnects between existing breakouts. Slide Updates.
  • Productivity Enhancements. NC pins assigned fillets will no longer be reported in the Shapes Without an Assigned Net report. Unsupported Prototype Functionality allows you to use new features and functions that are currently in a prototype state but are mature enough for use in production. Offset Move and Copy Update are now part of a suite of drafting commands.
  • Miscellaneous Enhancements. Updates include Bundle Visibility and IDX updates. The File – Change Editor command has been enhanced to display all product choices.

QIR 6

  • IPC 2581 Stackup Exchange. The ability to import stackup data using IPC-2581 has been introduced in 16.6 QIR 6. 
  • Route Interconnect Optimization. Auto Interactive Breakout Technology is an auto-interactive command designed to expedite the breakout of high pin count devices like BGAs and connectors. The Remove Tuning command automatically removes standard tuning bumps and phase bumps from cline routing. Dynamic Rat Suppression hides all rats except the selected trace to improve visibility as it relates to your routing path. 
  • Productivity Enhancements. Updates to Split Views, Move Component with Slide Etch, Drafting Updates, Dimensioning, File Locking Update, Find by Query, Unsupported Prototype Functionality, SPIF Enhancement 
  • RF PCB Enhancements. Autoplace Enhancements including Support for Placement of Modules and Restore Autoplacement Settings. Layout Enhancements including snap to pad edge function and cursor dynamics creation time has decreased during interactive snapping.

QIR 5

  • IPC-2581 Rev B Support. The Allegro PCB Editor provides support for the IPC-2581 Rev. B format. 
  • Interface-Aware Design. DDRx support with a suite of tools is referred to as Allegro Timing Environment (ATE), which includes Timing Vision, Auto Interactive Phase Tune, and Auto Interactive Delay Tune. 
  • Route Interconnect Optimization.  Scribble is a routing mode that allows you to scribble a route path onto the canvas. Auto-Interactive Phase Tune Update to include a new option. Uncoupled Bump Creation now permits the use of accordion bumps for phase tuning Diff Pairs. 
  • Productivity Enhancements. Updatest to Move Component – Slide Etch, Split Views, Drafting Updates, Snap Pick Updates, Named Text Blocks, PADS Translator Updates, Layer-Based Optimization for bundle-nets, and Unsupported Prototype Functionality. 
  • RF PCB Enhancements. RF PCB now supports MWO libraries.

QIR 4

  • Step Model Viewing Enhancements. The 3D viewer of Allegro PCB Editor has the capability of viewing footprint and mechanical models in more detail by use of STEP model mapping. Allegro PCB Editor provides the ability to export an Allegro PCB design as a STEP model. 
  • Route Interconnect Optimization. A major effort targeted at improving the productivity and efficiency aspects of the interactive routing environment continues.Upates to the Allegro Timing Environment, Timing Vision, Auto-Interactive Phase Tune (AiPT), and Auto-Interactive Delay Tuning (AiDT). 
  • Productivity Enhancements. Updates include Voids in Keepout Shapes, Artwork Control Form update, Allegro PDF Publisher, Relative Snapping, Ref-Des Layer Visibility Control, Dynamic Shapes, and Add Scan and Highlight update for Testprep. 
  • RF PCB Enhancements. Increased productivity with Layout Enhancements (Modify Connectivity and Enhanced Grouping Functionality), Autoplace Enhancements (Add Module Support and Enhanced Fix Placed Symbol Functionality), Discrete Library Translator Enhancements, Replicated block and module support, and Support for Processing Unit Scale Factors and Tune Parameters.

QIR 3

  • Step Model Support for accurate 3D viewing. The Allegro PCB Editor products currently provide 3D viewing of an Allegro board drawing based on the open drawings layer visibility and object selection. The 3D viewer provides a basic rendering of board geometry, conductors, via structures and component geometry with little or no detail also referred to as block style or skyscraper viewing. 
  • Route Interconnect Optimization. Updates to Auto- Interactive Breakout Technology (AiBT), Split View, Zoom Swap Views, Auto Interactive, Add Connect,and Detune. 
  • Productivity Enhancements. Improvements to Slide Enhancement, New Variable Restores Line Width Retention to legacy behavior, Allegro Drafting Prototypes, Delete by Line, Delete by Rectangle, Offset Copy, Offset Move, Add Perpendicular Line, and Help on Unsupported Prototypes. 
  • Database & Misc Enhancements. Updates include Pastemask DRC, Database Diary, Retain Pop-up window locations when using multiple monitors, Roaming Aligned with HDL, Missing Fillets Report 
  • RF PCB Enhancements. Layout Enhancements (Modify Connectivity, Snap, and Clearance), Selecting User Specified Connect Pin, RF Routing Enhancements (Line Width Retention, Automatic Layer Switching, Undo of Line Width Change), Autoplace Enhancements, and Discrete Library Translator Enhancements.

QIR 2

  • Route Interconnect Optimization. Updates to Auto-Interactive Phase Tune (AiPT) – High Speed Product Option, Timing Vision – High Speed Product Option, and Unsupported Prototype Menu. 
  • Productivity Enhancements. Highlight/Assign Color to Vias, Display-Measure support of angle between two objects, Display Segments over Voids, DRC marker – Link to Constraint Manager, Expand/Contract Shape updated to support Voids, Net assignment to multiple shapes, Placement Replication support for component level pin properties 
  • Database & Misc Enhancements. Database Locks, Database Tiering – New Open Drawing Message, Logo Import (Symbol Editor only), New Reports, Slot Notes

16.6 Release

  • Route Interconnect Optimization. Updates to Auto-Interactive Phase Tune (AiPT) – High Speed Product Option, Timing Vision – High Speed Product Option, and Unsupported Prototype Menu. 
  • Productivity Enhancements. Highlight/Assign Color to Vias, Display-Measure support of angle between two objects, Display Segments over Voids, DRC marker – Link to Constraint Manager, Expand/Contract Shape updated to support Voids, Net assignment to multiple shapes, Placement Replication support for component level pin properties 
  • Database & Misc Enhancements. Database Locks, Database Tiering – New Open Drawing Message, Logo Import (Symbol Editor only), New Reports, Slot Notes

OrCAD Capture

QIR 6

  • Windows 8.1 Support. OrCAD is officially supported on Windows 8.1

QIR 5

  • Rapid PSpice Model Association. Capture now supports instance-level, PSpice model assignment directly to components in the schematic editor. 
  • PSpice Library Search. Capture now provides an easy method to search through the installed library of simulation models / parts using PSpice Part Search. 
  • Capture View-Only Mode. New view-only mode allows any project / schematic files to be opened for review without consuming a license. 
  • Redefined Quick Place Menu. The Capture Place > PSpice Component menu has been updated with new items and sub-menus including; PSpice Ground, common discrete components, and new sources.

QIR 4

  • Display Properties Update. New display property option to display a value only if a value exists. Useful for commonly displayed properties like tolerance where you would not want to display the property name if a value does not exist. 
  • Capture View only Mode. Allows Capture to be opened in read-only mode and does not check out a license. Accessible through command line switch capture.exe -viewer 
  • Zero Pin Mechanical Parts. Mechanical parts with no pins like bar-codes, fiducials and mechanical holes can now be placed on the schematic and synced with the PCB 
  • SI Flow Updates. The Capture SI flow now supports Sigrity products as well as OrCAD PCB SI

QIR 3

  • Object Alignment. Support for horizontal and vertical alignment of objects on a group or signal object level. New alignment toolbar added as well. 
  • Object Distribution. Select and distribute objects evenly or horizontally. 
  • Library Refresh. If libraries are updated outside Capture during an active session users can now perform a library refresh to display the updated information 
  • Schematic Page Name Property in Titleblock. Titleblock now supports a new system property “Page Name”. The “Page Name” property behaves like the “Schematic Name” property available in previous releases. Any change to the page name automatically synchronizes and updates the value of the property. 
  • SI Flow Update (XNet View). Users can now easily view a filtered list of defined XNets in the current design. View provides data on the XNet included the flatnets that make up the XNets. 
  • New NetGroup Display Options. Can now set NetGroup to display the definition of the NetGroup only if the name of the NetGroup is different from the NetGroup instance.

QIR 2

  • Common Property Text Justification. You can now justify comment text and the text of displayed properties of any Capture object, such as Parts, Off Page Connectors, and Ports. 
  • Tcl Updates. New Tcl scripting API updates are available for variant customized variables in the titleblock, visibility control on NetGroup alias, and access to project libraries. 
  • Design Date Format Options. Two new options for data format display 
  • Convert Views.  Convert Views supported in PCB Editor netlisting

16.6 Release

  • Capture – PCB SI Integration and Flow. With product integration comes a new bi-directional schematic entry/signal integrity flow that allows electrical engineers to explore circuit topologies, develop constraints, and analyze signal integrity. 
  • Quick-Place for Common Components. A new menu, Place >PSpice Component, enables quick-place for commonly used schematic or simulation components.  The menu items list of components is user-configurable and has been pre-populated with PSpice® simulation devices (passive, discrete, sources, digital). 
  • User-Configurable Menus and Toolbars. Menus, toolbars, and icons in OrCAD Capture, PSpice Advanced Analysis, and Model Editor can now be customized. This makes it possible to run any Tcl method or script from the menus. 
  • Enhancements to the Find Function. The Find function now allows searches for parts by value of a given property (e.g. Property Name=Value) or use of a regular expression as the search string. For example, to search for components with designators starting with C or R and followed by any number between 2 and 9, use the search string Part Reference=(C|R)[2-9]. 
  • NetGroup Enhancements. The NetGroup use model is now aligned with the Bus use model for intuitiveness and consistency. Enhancements areas include: assign a NetGroup to a Bus, reorder pins in an unnamed NetGroup, add and remove pins from a NetGroup, visible NetGroup references, and find NetGroup references. 
  • Enhanced Save Function for Design and Library. Pages that are changed and need to be saved are now marked by an asterisk (*) in the Capture Project Manager. When a save is initiated, the marked pages are saved. 
  • Global Replace for OffPage. The Find and Replace dialog box (Edit> Global Replace) has a new option, OffPage Connector, to find and replace OffPage connectors. 
  • Preserve “User-Assigned” Designator. Reference designator management improvements now track the user-modified references and allow finer end-user control over managing the part references for the entire design. A reference designator can be interactively set as user-assigned through the newly added “User-Assigned” flag to preserve designators and references in conjunction with the Preserve Designator and Preserve User-Assigned Valid References in the Annotate window. Capture will also mark a reference designator as user-assigned if the reference is manually changed in Property Editor, manually changed in the schematic canvas, or changed by the board through back-annotation. 
  • Design Level Auto Reference. In addition to schematic-level annotation, design-level annotation is now available by selecting the Design Level option in the Miscellaneous tab of the Preferences dialog box. An option to preserve references when copying is also available. 
  • Browsing/Viewing Designs Created in Earlier Versions. Designs created using earlier versions of Capture can now be opened and viewed without requiring the design to be uprev’ed. Such designs only need to be uprev’ed when the design is actually saved. 
  • Closing All Tabs. Canvas tabs can now all be closed, or all but this tab closed with an RMB selection. Right-click on the tab and choose the appropriate option (Close, Close All Tabs, or Close All Tabs But This. 
  • Custom Design Rule Check (DRC). Though Tcl scripting, user-defined schematic and circuit checks can be created and added to the Capture DRC routines. Several R&D examples include checks for hanging wires, device pin mismatches, overlapping wires, reference prefix mismatches, port-pin mismatches, and shorted discrete parts. 
  • Project Save As Enhancements. While saving a project in 16.6, a project name that is different from the design name can be specified to mimic the manual process of copying/moving a product from one hard-drive location to another. Options include the ability to copy/move all referenced files, ensuring that all links are updated while saving. 
  • RefDes Support Alignment. Capture and CIS now handle references and designators in the same manner, eliminating the need for manual Reference Designator corrections in the CIS database and BOMs. CIS now supports all reference designator formats including as U2N, C1_R, C12-1, R7-TOP, MP_2V5_REF, and TP3V3_0. Also, the reference designator for multi-packages is consistent (e.g. MP_2V5_REF will be MP_2V5_REF not MP_2V5_REFA).
  • Linking External Design Parts. Referenced parts of the external design can now be linked at the group or subgroup level. 
  • CIS Performance Increase. The overall performance for CIS operations, especially when dealing with very large databases or queries, has been significantly improved. 
  • Tcl Customization for CIS Explorer. CIS Explorer can be custom-configured with user-definable actions and capabilities. (For example, customized part placement checks can disable placement of an EOL part or provide a warning if part procurement has a long lead time). Query result rows can also be customized.  (For example, rows can be highlighted blue for recommended parts or red for parts not recommended or allowed.) 
  • CIS Multi-Value Support. Any CIS field can now be set as multi-valued for component instances with numerous information or content sources (e.g. lists for multiple datasheets/application notes or multiple PSpice models for a component).

Allegro Design Entry HDL

QIR 8

  • Port Groups. Support for port groups or an interface port on a hierarchical symbol that corresponds to a net group used in the lower-level schematic. 
  • Variant Operations in Design Entry HDL. Variant-related tasks such as creating, editing, and deleting variants, marking components to variants, replacing components in a variant can now be performed in Design Entry HDL itself. 
  • Replace Component Validation in Variant Editor. When you now replace a component in Variant Editor or in the schematic variant view, Variant Editor checks whether the two components–the component that is being replaced and the component that will replace the selected component–have the same or compatible footprints, that is, JEDEC_TYPE properties. If the footprints are not compatible, a warning message is displayed.

QIR 7

  • Port Groups. Support for port groups or an interface port on a hierarchical symbol that corresponds to a net group used in the lower-level schematic. 
  • Variant Operations in Design Entry HDL. Variant-related tasks such as creating, editing, and deleting variants, marking components to variants, replacing components in a variant can now be performed in Design Entry HDL itself. 
  • Replace Component Validation in Variant Editor. When you now replace a component in Variant Editor or in the schematic variant view, Variant Editor checks whether the two components–the component that is being replaced and the component that will replace the selected component–have the same or compatible footprints, that is, JEDEC_TYPE properties. If the footprints are not compatible, a warning message is displayed.

Version 16.5

Products Covered: Allegro Layout Editors | Capture | Allegro Design Entry HDL

Allegro Layout Editors

16.5

  • Embedded Component Design: Enhancements including updates to Licensing, Front to Back Flow Support, Setup, Key Terminology, Design Rule Checks, and Best Practice Paper.
  • Graphical User Interface: Updates including Highlighting With Stipple Patterns, Dynamic and Static Shape Display, Highlighting Fixed Objects, Status Bar Updates, 3-D Viewer Update, Data Tip Setup, and Data Tip Display. Etch Edit Enhancements. Upates to Differential Phase Tuning, Trace Tapering, Group Route Via Patterns, Diff Pair Routing -, Transitions at Region Boundary, Pad Exit Behavior, HDI Via Labels, HDI Via-Via Line Fattening, Delete Via Structures, and Copy/Move Stacked Vias.
  • Intelligent PDF Output: This tool exports Allegro board data in a PDF document with intelligent data for components, nets, and test points. You can specify the graphical Class/subclass layers that can be viewed and the properties that are to be extracted in the PDF.
  • Associative Dimensioning: The Allegro dimensioning capabilities have been enhanced so that when a dimension is created involving one or more design database objects, internally, the dimension remains associated with these objects. Subsequent editing operations, such as the moving of an object, can then appropriately and automatically update any dimensions that are associated with that object.
  • Design for Manufacturing: Updates include DFA Enhancements (Side-End and End-Side support), DFA Usability, Minimum Metal to Metal, Clearance DRC, Duplicate Drill DRC, Cross Section Chart, and Backdrill Enhancement (Any Layer to Any Layer).
  • DRC Updates: Starting this release, the behavior of the Max Neck Length DRC is changed. Now the DRC flags an error if the cumulative length of necked sections exceeds the prescribed Max Neck Length value.
  • ECAD-MCAD Flow: Incremental data exchange with IDX.
  • Database and Misc Enhancements: Updates include Database Locking, Multi-threading Support, DBDOCTOR, Downrev to 16.3, DBSTAT, Same Net, Constraint Set update, Symbol Editor, Refresh Symbol, Modules and Locked Property, Techfile, Design Status, Color, Artwork, Thieving, Create Detail, Display Measure, Shape Copy, User Defined Mask Layers — Mirror support, Place Replicate — Support for Single Symbol, Placement Files, Design Partitioning, Polygon Select, Undo/Redo Buffer, Capture Canvas Image, Zoom Button in Pick Dialog, New Variables, New Properties, Modified Properties, Deleted Properties, Reports, IDF Out, Symbol Export, Data Migration, Script Migration, and Skill Enhancements.
  • RF PCB Enhancements: Updates include Usability Enhancements, IFF Interface Enhancements (Layer mapping for non-etch layers, Hierarchical component importing, RefDes Auto-synch) and Layout Enhancements (Breaking RF Components, Inserting RF Components, Converting RF Components, Shape to Component Enhancements, RF Push Enhancements).

OrCAD Capture

16.5

  • Graphical Operation Locking (GOp): The GOp locking feature in Capture now allows you to lock the different parts of a schematic design. Lock objects on a page, folder, or even the complete design. This feature prevents inadvertently moving or deleting parts of a design that are locked. Designs requiring alteration will need to be unlocked before any changes are made.
  • Placement Report: Generate a report of the X and Y locations of the placement of the parts on a schematic. This report, generated as a .CSV file, provides details of the parts including; Reference Designator, Part Name, Schematic Name, Sheet Number, File System Location of the Part Library, and X and Y co-ordinate location.
  • Find Results Report: After executing the Find command on a design, generate a report for the results from the command. By running the Find command to search for different types of objects in a design, the search results display in different tabs of the Find window, allowing you to export the data from each tab.
  • Net Groups: OrCAD Capture introduces the concept of the NetGroup that allows you to create groups of nets. A NetGroup can include a group of scalar nets, vector nets, or a combination of both. Capture allows you to create Named NetGroups that can be used across a design or exported to other designs. Alternatively, for one-time use, you can create an Unnamed/Adhoc NetGroup. The new NetGroup Connector can be used to intelligently merge and tap out signals. It can also be used to generate net names for connected signals.
  • CIS.INI Settings: While the Capture INI settings are always dynamic, the CIS settings are more or less static and usually do not change after the initial CIS database related setup. You may often need to clear out and reinitialize your Capture INI settings, but may still want to retain the CIS settings. To allow this, OrCAD 16.5 now retains the CIS INI settings in a separate back-up file. This file retains the CIS INI settings that Capture will retrieve when it re-initializes the Capture INI settings.
  • Partial Design Simulation: The 16.5 release comes with the productivity enhancing feature of partial design simulation. You can now identify individual components of any design, and, using the partial design simulation feature, simulate only selected portions. Using this feature, you can simulate different circuits in the design with different simulation profiles. You can also netlist only a particular portion of the design. In addition, you can compare and merge portions of a design quickly.
EMA Design Automation