Cadence OrCAD FPGA System Planner

Cadence OrCAD FPGA System Planner
OrCAD FPGA System Planner provides FPGA-PCB co-design that allows users to create optimum, correct-by-construction pin assignments in a complete, scalable solution.

The Cadence® OrCAD® FPGA System Planner helps designers utilize complex FPGAs with advanced pin assignment technology that automates manual processes. FPGA pin assignment is synthesized automatically based on user-specified, interface-based connectivity (design intent), as well as FPGA pin assignment rules (FPGA-rules), and actual placement of FPGAs on PCB (relative placement). The FPGA Planner is integrated with both OrCAD Capture and OrCAD PCB Editor. It reads and creates OrCAD Capture schematics and symbols. FPGA pin assignments are synthesized automatically based on user-specified, interface-based connectivity (design intent), as well as FPGA pin assignment rules (FPGA-rules), and actual placement of FPGAs on PCB (relative placement). This produces higher quality designs that utilize a system level understanding of the project for better optimization.

Benefits:
  • Scalable, cost-effective FPGA-PCB co-design solution from OrCAD to Cadence Allegro® GXL
  • Shortens time for optimum initial pin assignment, accelerating PCB design schedules
  • Accelerates integration of FPGAs with OrCAD PCB design creation environments
  • Eliminates unnecessary, frustrating design iterations during the PCB layout process
  • Eliminates unnecessary physical prototype iterations due to FPGA pin assignment errors
  • Reduces PCB layer count through placement aware pin assignment and optimization
Specify Connectivity
The OrCAD FPGA System Planner allows users to specify connectivity between components within the FPGA sub-system at a higher level through interface definitions.
FPGA Device Rules
The OrCAD FPGA System Planner includes a library of device-accurate FPGA models that incorporate pin assignment rules and electrical rules...
Extensive Scalability
Scalability is a key component of the OrCAD and Allegro FPGA System Planners; it allows designers to pay for just the level of capabilities they need.
Integration With FPGA Vendor Data
Integration with FPGA design tools for generating and reading supported FPGA vendors’ pin assignment constraint files.
Creation of System Placement and Floorplan Views
FPGA System Placement Views can be created using OrCAD and Allegro PCB Editor footprints.
DescriptionType
The Cadence® Allegro® FPGA System Planner addresses the challenges that engineers encounter when designing one or more large-pin-count FPGAs on the PCB board.
DataSheet (PDF)
Current solutions for application-specific integrated circuit (ASIC) prototyping limit the designers choices. Cadence® Allegro® FPGA System Planner offers a simplified and more flexible approach to ASIC prototyping.
Application Note
Allegro FPGA System Planner helped JDSU achieve a 30% to 40% time savings in their front-end design process. In addition, they realized a 50% time reduction in routing high-speed signals.
Customer Success Story
In this paper Cadence offers recommendations for power-supply connections, pin selections and assignments, and other tips and methodologies to help customers design high-quality FPGA-based systems.
DataSheet (PDF)
Active-HDL is an integrated FPGA Design and Simulation solution, with design entry, a high-performance mixed-language simulator and an easy-to-use, multi-vendor FPGA flow manager.
DataSheet (PDF)
The Cadence® OrCAD® FPGA System Planner addresses the challenges that engineers encounter when designing large-pin-count FPGAs on the PCB board.
DataSheet (PDF)
With the help of Cadence Software, VeriSilicon shortened their FPGA-based ASIC prototype development time by 75% and completed optimal pin assignment in one week vs. at least one month previously.
Customer Success Story
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