Cadence® OrCAD® Signal Explorer provides a scalable, cost-effective pre- and post-layout
system interconnect design and analysis environment. Signal Explorer is tightly integrated
with Cadence OrCAD PCB Editor and is a component of the Cadence OrCAD PCB Designer
suites. As your level of signal integrity challenges and sophistication grows, Signal Explorer
provides an easy upgrade path to the advanced Cadence Allegro PSB SI technologies.
Signal Explorer addresses the challenges created as a result of increasing design density, complexity, and faster
edge rates by enabling designers to address signal integrity (SI) issues throughout the design process. This
approach allows design teams to eliminate time-consuming simulate-fix-simulate iterations at the back-end of a
design process.
Signal Explorer allows users to weigh the trade-offs involved in routing choices (rules) that affect cost relative to
electrical performance and reliability. Once developed, these optimum constraints then drive the physical layout
and routing of the PCB.
- Provides cost-effective, scalable, pre- and post-layout system interconnect design and analysis
- Improves circuit performance
- Increases circuit reliability
- Eliminates the need to translate designs databases to run simulations
- Saves time via a virtual prototyping environment that is seamlessly integrated with OrCAD PCB Editor
| Macro modeling support (DML) |
Graphical topology editor |
| IBIS 4.2 support |
Lossy transmission lines |
| IBIS ICM model support |
Coupled (3 net) simulation |
| Spectre-to-DML conversion |
Differential pair exploration and simulation |
| HSPICE-to-IBIS conversion |
|
Signal Explorer contains a module for pre-route topology design and analysis even before a schematic is created
(the SigXplorer module). This type of analysis is common at the earliest stages of the design cycle when
designers assess the impact of using a new device technology or of increasing bus transfer rate. SigXplorer can
be used to build and validate detailed electrical topology models and prove the viability of a new technology—
before the detailed design process begins.
Signal Explorer provides a SPICE-based simulation environment for PCB SI analysis. It consists of the Tlsim
simulation engine, the SigWave waveform display, the Device Modeling Language (DML), translators from other
modeling formats, and a library model editing/management subsystem. The SigWave module provides
capabilities to import waveform data both directly from various standard test equipment formats as well as from
the output formats of popular SI analysis tools.
Signal Explorer includes a model integrity module that allows designers to create, manipulate, and validate
models quickly in an easy-to use editing environment. Device model formats supported include:
- IBIS 4.2 External Model support for Verilog®-A, Cadence Spectre®, HSPICE, Cadence eSpice models
- IBIS ICM package and connector models
- SPICE device models
- Cadence Device Modeling Language (DML)
- Mentor/Quad XTK