Designers reduce board layout and placement time from weeks to minutes through CircuitSpace® AutoClustering™ technology, intelligent design (IP) reuse, and replication. Reductions in PCB design time have a direct impact on time-to-market for new products, which directly correlates to profitability.
CircuitSpace breaks down the current 'click and drag' placement tedium and accelerates the whole design process. CircuitSpace seamlessly integrates with Cadence® Allegro® PCB Editor or OrCAD® PCB Editor and allows users to achieve board layouts in a fraction of the time it would take to complete by hand.
CircuitSpace implements a hierarchical approach to printed circuit board design through enhanced AutoClustering and replication technologies. With the AutoCluster feature designers achieve the same results that, by hand, would typically require tedious, time-consuming and error-prone effort. CircuitSpace extracts data directly from the schematic and components are automatically gathered into interconnected groups called clusters. Once a cluster is created a rough placement of the components is performed, simplifying a designer’s task of manual placement. CircuitSpace also expedites the design process through the use of template generation for global library usage across divisions, template usage with and without etch, automated layout reference designator propagation and automated change report between layout designs.
CircuitSpace makes it easy to duplicate layout decisions and apply layouts to other boards without mapping reference designators or net names. Designed and tested clusters can be reproduced in a design, or even applied to a different board. Eliminate redundant work by referencing existing designs and repurposing clusters in new designs. Once available in the new design, create replicas of the repurposed clusters and update as a group.
Designs are revised over time, during the course of a project, and from board to board. CircuitSpace propagates changes and helps designers manage them effectively. Checkpoint reports describe a board’s current state, enumerating clusters, members and nets. Designers can save and compare design checkpoints at any time during a design project. Comparison reports identify the difference between a checkpoint report and a board, or another check point report. Designers can review the additions to a cluster’s membership before modifying the actual cluster.
- Create functional groups of components based on design information through AutoClustering
- Bi-directional communication between Cadence Allegro and OrCAD PCB Editor and a (PDF) schematic is possible through cross-probing
- Create multiple replicas of a source cluster's net topology
- Propagate cluster membership, placement and shape changes to specified clusters
- Save a design checkpoint at any time and compare it against other checkpoints
- Create a cluster from a specified group of components
- Propagate cluster reference designator text locations to target clusters
- Create templates containing a cluster’s membership, net topology, and placement information
- Reuse design templates in new or legacy designs
CircuitSpace 4.0 offers new features that expedite the PCB layout process. These features include the ability to review a reuse template graphically before applying it to the design, the ability to swap two cluster positions by selection, and support for AutoClustering based on a PDF version of the schematic, among others. For a detailed explanation of the new features, please visit
www.ema-eda.com/circuitspace4.