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Cadence® Allegro® system interconnect design platform provides constraint-driven flows that speed product development—from concept and capture to manufacturing. The latest Allegro 16.2 release enhances these solutions with new capabilities that address current and future business-driven technology challenges, including miniaturization, shorter product lifecycles, increasing design speeds, and environmental concerns.
The new technology helps deliver shorter, more predictable design cycles for PCB designs. With significant improvements for designers using high-density interconnect (HDI), the technology will be of particular value to customers in the high-end consumer electronics market, as well as those in segments such as computing and networking where users are seeking a constraint-driven HDI design flow.
New technology introduced in Allegro PCB Editor for HDI designs includes new objects, an extensive set of new rules for micro-vias, an enhanced via-transition use model, and changes to the entire PCB design flow to enable a comprehensive constraint-driven HDI design flow. Design partitioning has been enhanced with new capabilities for partitioning the design horizontally and adding soft boundaries to allow users to work in parallel more efficiently, further shortening the design cycle.
Allegro Design Entry HDL is a design environment that supports behavioral and structural design descriptions captured in text and graphics. It includes block-editing functions for quick architectural design. This schematic-based design entry solution is fully integrated within the Allegro platform.
Automatic Table of Contents Generator - In many of the designs you create, the first sheet of the schematic contains the table of contents (TOC). A TOC provides a quick view of the design contents in single or multiple pages. Allegro DE-HDL 16.2 provides functionality for creating and automatically updating TOC with design information. This feature replaces any indigenous solutions that you might have been using until now. The automatic TOC generator feature saves you design time, as it does not require any manual validation.
Cross-References as Links – The Cross-Referencer (CRefer) utility is used for verification and debugging of designs by following a signal's path throughout the design. CRefer traces out the flow of a signal all over the design and by annotating some properties on the schematic makes the signal navigation simpler. In the 16.2 release, these property values are converted to hyperlinks. You can now click these links and navigate to the location as specified in the property value.
Physical and Spacing Constraints - The 16.2 release allows you to connect the Allegro Constraint Manager to Allegro DE-HDL. You can create, view, edit, and assign physical and spacing constraints to a group of nets or directly to nets in addition to electrical constraints.
Show Unconnected Pins - Allegro DE-HDL now provides a method to quickly identify all the components which have unconnected pins.
Layout-Driven RF Design - In release 16.2, a layout-driven RF PCB Import flow has been integrated with the traditional import physical flow. If your designs contain RF circuitry, you can synchronize the RF circuitry in the schematic with the layout.
Integrated with the Cadence Allegro PCB design and route suite, Cadence Allegro PCB SI provides advanced signal integrity (SI) analysis both pre- and post-layout. Operating early in the design cycle allows for “what-if” scenarios, sets more accurate design constraints, and reduces design iterations. Allegro PCB SI reads and writes directly to the editor database for fast, accurate integration of results. Along with a SPICE-based simulator, it provides behavioral modeling and an embedded field solver with a robust modeling language. Bus architecture can be explored pre-layout to compare alternatives, or post-layout for a comprehensive analysis of all associated signals. The Cadence Allegro PCB PI Option provides modeling of all power distribution characteristics.
Electromagnetic Solution 2D Full Wave Field Solver - EMS2D in Allegro PCB SI and Cadence OrCAD® Signal Explorer provides the full-frequency range analysis from DC, through the middle frequency range which covers the skin effect, to the THz range of the electromagnetic interactions which address resonances, radiations and EM signal integrity issues.
EMS2D is implemented using the finite element method (FEM), which complements the Allegro PCB SI moment-based BEM2D field solver. EMS2D combines multiple EM computation modules, static, quasi-TEM, and full-wave analysis. Additionally, EMS2D is able to analyze arbitrary transmission line-type and waveguide structures over PCB cross-sections and provide characterized models in RLGC and/or S-Parameter format.
Enhanced Etch Factor Support - This feature is an enhancement of the functionality that defines a trapezoidal cross-section for clines on conductor and plane layers. This capability differs from the existing trapezoidal_angle_in_degree environment variable in the following respects: allows different degree of angle for clines on different layers, allows you to set the degree of angle for either the top or the bottom of the cline, and supports graphical displays that allow you to view where you apply the angle and line width. Additionally, if you specify an etch angle factor for a cline within a CPW structure, EMS2D automatically applies the specified angle value to the bottom edges of the surrounding ground shapes when the angle is something other than 90 degrees.
Channel Analysis Developer's Toolkit – A new Channel Analysis Developer’s Toolkit is included with the 16.2 release. It contains sample topology files and DML models that let you analyze a real system consisting of advanced SERDES devices and interconnect structures from chip to board to package within the Allegro PCB SI and Cadence SiP SI environments.
ICM Support - Model Integrity now provides complete support for the IBIS interconnect modeling specification and the ability to translate ICM model syntax to ESpice blackbox or PackageModel DML formats for use in simulations.
Non-Native Database Support - For system-level configurations, you can now open designs created in other applications. For example, Allegro PCB SI can open a .mcm design created in Cadence Allegro Package Designer or a .sip design created in SiP solutions. Because designs created in another tool may not contain signal integrity data that your application requires (voltage properties, cross-section data, model assignments, etc.), only limited editing of the non-native drawing is allowed.
Power Integrity for Packaging – You can now model and analyze power delivery network systems for your package designs in a similar manner as you do for board analysis, using the Allegro Power Integrity (PI) functionality. You can configure parameters for field solving and 3-D modeling as prerequisites for setting target impedance for a selected power net, assigning port types, grouping pins, and identifying current profile and/or simple, single excitation sources for die pins. In addition, you can place decoupling capacitors (decaps) in your designs and extract equivalent circuits for simulation. Together with Allegro PCB PI for SiP Solutions/Allegro Package Designer and PCB designs, Allegro PCB PI for packaging provides a total chip – package – board co-design flow.
Eye Mask and Measurement Enhancements - SigWave now lets you create eye masks that you can save in .sim files and view/edit when you display the waveform in Eye Diagram mode. The eye masks you create can be embedded in DML models and used in all standard, bus analysis, and channel analysis simulations.
Cadence Allegro PCB Editor 16.2 release focuses on productivity improvements in HDI design, etch edit and component placement, color and graphics, and manufacturing applications. The constraint driven flow has been enhanced to better support the diverse set of rules required for HDI design.
Constraint-driven HDI Flow - A constraint-driven HDI design flow for build-up designs to accelerate miniaturization is introduced in this release. With ever-decreasing pin-pitch BGAs it is becoming impossible to drill a through hole via within the ball grid. Allegro constraint-driven HDI features a proven, robust constraint-driven PCB design flow; comprehensive set of design rules for all different styles of HDI designs from a hybrid build-up-core combination to a complete build-up process such as ALIVH; automation for adding HDI interconnect to shorten time to create correct-by-construction designs.
Design Partitioning Enhancements - Design partitioning is now available to both PCB and Packaging products and better equipped to handle bus-intensive and HDI designs. Partition strategy can now be both vertical and horizontal, which allows team members to work under and over each other. The addition of soft nets permits partition designers to route across boundaries.
Differential Pair Enhancements - Differential pair line width and gap can now be driven by constraint region rules. The Physical domain has been enhanced to include additional diff pair rules (minimum line spacing, tolerance) allowing variance by layer. Diff pair pin-swapping options, polarity, and pair have been added to the swap application and are driven entirely by library pin group assignments.
Etch Edit Applications - A new add-via methodology based on the concept of multiple alternate layers is introduced in 16.2. The working layer model in combination with a new via popup GUI, localizes the steps of layer transition near the point of occurrence. A major benefit of the new Working Layer model is to automatically or semi-automatically add sequential blind and buried vias on the path to the destination layer.
Dynamic Unused Pad Suppression - By removing pads, higher routing densities are achieved by allowing traces to be closer to the edge of the hole. On HDI designs, candidates for pad removal can be the unused internal layer pads of the core via. The Unused Pad Suppression user interface controls the suppression state for pins and vias. Suppression can be applied to any or all of the inner signal subclasses.
Drill Hole to Metal DRC – A new class of hole-based checks, supported in both spacing and same net domains of Allegro Constraint Manager, provides the DRC capability when Unused Pad Suppression is enabled or pad definitions are set to null. A hole-to-metal check occurs only when the respective hole is void of pads on conducting layers. When pads are present, the hole check yields to the convention pin and via checks.
Dynamic Filleting - The gloss-based fillet application has been enhanced to support the dynamic updating of fillets on pins, vias or T-junctions. The application continues to support the interactive or batch mode options as well as the parameters currently in place. The new dynamic option offers the convenience of filleting during interactive etch editing with no additional steps. When this option is enabled, fillets are added when a connection is made to an element or deleted when removed.
Placement Application Mode - Efforts in improving tool usability and performance have been a strategic part of 16.0 releases. This effort continues in 16.2 where the focus is on component applications. The foundation for such enhancements begins with the introduction of the fourth application mode called placement application mode, a tuned, high-performance editing environment designed to increase efficiency during component placement sessions.
Placement Replication - The re-use and repetition of circuit blocks in the Cadence flow has traditionally been accomplished with the Design Re-Use Module application, which requires both front and back end participation and is limited to Cadence-supported schematic systems. Building on that technology, a less-restrictive, intuitive use model is desired that limits the dependency of front end requirements to just the traditional netlist. The placement of a "seed" circuit followed by a selection of randomly placed components generates the replicated circuits based on common device types, symbol names, values, and connectivity. Circuits that often get replicated are memory modules, IO channels and capacitor schemes associated with high pin count devices.
Advanced Routing Options for PCB Design XL and PCB SI - Allegro PCB Editor provides advanced routing options permitting you to graphically develop, analyze, and even generate complete routing solutions for interconnect flows in your design. The following are licensed advanced routing options available with the Allegro PCB Design XL and Allegro PCB SI products:
- Flow Designer, GRE Feasibility, GRE (Global Route Environment)
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