Cadence® OrCAD® Signal Explorer addresses the challenges created as a result of increasing design density, complexity, and faster edge rates by enabling designers to address signal integrity (SI) issues throughout the design process. This approach allows design teams to eliminate time-consuming design iterations and potential re-spins by implementing a correct by construction process.

Beyond ensuring design correctness and manufacturability, users can weigh early-on and with a high degree of accuracy the trade-offs involved in routing choices (rules) that affect cost relative to electrical performance and reliability. Once developed, these optimum constraints then drive the physical layout and routing of the PCB.  This provides not only security in a functional design, but a design that is optimized to best meet your electrical and financial requirements.