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The Cadence® OrCAD® FPGA System Planner addresses the challenges that engineers encounter when designing one or more large pin-count FPGAs on the printed circuit board. These challenges include creating the initial pin assignment, integrating with the schematic, and ensuring the device is routable on the board. OrCAD FPGA System Planner shortens the time required to design-in complex, large pin-count FPGAs by allowing entry of design intent at the system level and then completely automating the pin assignment over multiple FPGAs at once, greatly reducing the risk of manual error. This solution reduces the number of pin optimization iterations during PCB layout and minimizes the number of layers required to route the FPGA on a PCB design.
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