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How to Perform Signal Integrity Analysis on Nets in OrCAD PCB Designer Professional

This tutorial will provide step-by-step instructions on how to use the SI Design Setup wizard and SigXplorer included in OrCAD PCB Designer Professional to perform analysis for your high-speed signals in version 17.4. To learn this tutorial for older versions of OrCAD PCB Designer Professional, check out this blog post. If you would like to follow along, you can download the design files here.

SI Design Setup is a utility used to bridge the physical design representation in the board layout and the equivalent electrical representation in SigXplorer. This wizard will walk you through all the necessary information and steps to perform SI simulations.

SigXplorer is a SPICE based simulator that aids in exploring, identifying, and solving the adverse analog effects of a digital system. The easy to use workflow and interface allows you to create "what if" scenarios on critical high-speed signal on your board.

1. Open Signal_Integrity.brd in OrCAD PCB Designer Professional.

Signal_Integrity.brd in OrCAD PCB Designer Professional

2. Right click in the canvas and select SI Design Setup or Setup > More > SI Design Setup from the menu.

This will invoke the Setup Category Selection which allows you to select the categories on which to perform set up operations.

Setup Category Selection

3. Leave all the boxed checked and select Next to Setup XNet Selection.

In the Setup XNet Selection window, select the XNets or Nets in which the operations are to be run.

Note: An Extended Net or XNet is a physical net that passes through discrete components. The physical net in the PCB is represented by an electrical equivalent (topology) called an XNet.

Setup Xnet Selection

4. Expand tree and select XNet MCLK.


5. Select Next to Setup Library Search Directories.

Here you verify that all the directories containing the required model files are available for use. You can change the sequence in which the directories are searched to locate a model or add a new directory.

Setup Library File Extensions

6. Leave the defaults and select Next to Setup Library File Extensions.

Here you set up the file extensions used for each type of model file.

Setup Working Libraries

7. Leave the defaults and select Next to the Setup Working Libraries.

This window displays the library files found in the specified search directories. Here you can select which libraries are to be used as working libraries for new models to be stored. 

8. Leave the defaults and select Next to Setup Power and Ground.

This window is used for specifying the setup of power and ground nets by assigning voltage. Voltages have been automatically assigned. Ensure the following values:

- AGND= 0V
- GND= 0V

- V+12=12V
- V12N=12V

- VCC= 5V

SI Design Audit

9. Select Next. The SI Design Audit will appear with warnings. Select All under Ignore Errors.

Setup Design Cross-Section

10. Click OK to Setup Design Cross-Section.

The Setup Design Cross-Section window gives you the option to edit or update the design. You can manually edit the exisiting cross-section, load a cross-section from another design or technology file.

Setup Component Classes

11. Select Next to Setup Component Class.

In the Setup Component Class window, define the types of components in the analysis. You can classify components as IC, Discrete, or IO. Components have been automatically classified.

Notes: IC Class is an active component, such as a driver or receiver. Discrete Class is a passive component such as resistors, capacitors and inductors. IO class is input and output devices, such as connectors.

If you need to change a classification, click the box next to the component and select the new classification under “Change Selected Component Devices To”.

If models need to be assigned the “Assigning Models to Component” Window will be included next in the SI Design Setup Wizard. Default models are automatically assigned.

Setup Diff Pairs

12. Select Next to Setup Differential Pairs.

The Setup Differential Pairs window displays user-defined and mode-defined differential pairs for the selected XNet or Nets. For this tutorial, no differential pairs need to be created.

Setup SI Simulations

13. Select Next to Setup SI Simulations. 

The Setup SI Simulations window lets you specify the simulations to be performed and the simulators to be used.

14. Check Reflection and select Next.

Setup Complete

15. Select Finish.

Topology Extract

16. Select Tools > Topology Extract from the menu.


17. Browse to MCLK or select the MCLK net in the schematic.

18. Check the box next to Include Routed Interconnect.

Note: By selecting Include Routed Interconnect, accurate models of the physical traces and vias from your board will be included in the simulation rather than ignored.

19. Select View. This will activate the SigXplorer Window.

Stimulus Pulse

20. Select the driving pin, U5Right click and select Stimulus > Pulse.

Analyze Simulate

21. Run the simulation by selecting Analyze > Simulate from the menu or on the Signal Simulate button on the toolbar. This will bring up the SigWave Window.

SigWave Window

22. View the generated waveform. From the simulation, we can see that the circuit is overdamped. Adjust the value of Resistor R5 to correct this. 

Resistor R5

23. Return to the SigXplorer Window. Expand the parameters window and change the resistance value of R5 to 50 Ohm.

50 Ohm

24. Re-simulate the circuit by selecting Analyze > Simulate from the menu or the Signal Simulate button on the toolbar. This will generate a new waveform in the SigWave window.

Notes: Models can be changed and edited in OrCAD PCB Designer Professional menu:

- Analyze > Model Browser: set default library paths or add new libraries.
- Analyze > Model Assignment: change model assignments on the parts in your design.
- Analyze > Preferences: change any other defaults.

With only OrCAD PCB Designer Professional, you can perform signal integrity analysis in your design. The SI Design Setup walks you through the necessary steps and configurations needed for analysis of your high-speed nets. Once the created topology is extracted to SigXplorer, “what-if” scenarios can be reviewed, and adjustments can be made.