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EMA TimingDesigner Integrated with Cadence Allegro Sigrity for DDRx Sign-Off
EMA Design Automation (ema-eda.com), a full-service provider of Electronic Design Automation (EDA) solutions, today announced TimingDesigner 9.4, which is tightly integrated with the Cadence® Allegro® Sigrity™ SI solution to provide a unique, highly-automated timing closure environment for DDRx interface design and sign-off. “This integration allows the Sigrity solution to automatically export cycle-accurate timing simulation results to TimingDesigner for graphical viewing and analysis,” said Manny Marcano, president and CEO of EMA. “This is the only solution on the market which combines power-aware sign-off-level simulation accuracy with fully parameterized timing diagrams to ensure DDRx sign-off success.”
One of the larger challenges with DDRx design is the amount of data that needs to be analyzed to ensure a working system. Thousands of measurements must be taken by the simulation tool to help the designer qualify their interface. The majority of these measurements are relational in nature and require an understanding of all the signals involved to properly confirm that the requirement being measured has passed. Without proper context it can be very difficult to fully understand the implications of the simulation results and their effects on system timing.
Competitive simulation environments only provide the designer with a large spreadsheet consisting of a massive amount of data but no context with which to assess compliance or document timing closure. TimingDesigner is able to bring the Sigrity power-aware analysis data sets into context using timing diagrams to display the data in a visual format. The design team can then quickly, and with a high degree of confidence, identify potential problems in context and even make on-the-fly adjustments in TimingDesigner to test potential solutions before re-simulating or making a change in implementation. Upon signoff, TimingDesigner provides DDRx interface documentation showing the timing margin between all critical interface signals.
“Achieving reliable DDRx signoff is a significant challenge for our customers,” said Vinod Kariat, vice president of R&D for Simulation Products at Cadence Design Systems. “By collaborating with EMA, we are able to provide this unique DDRx timing solution leveraging the unparalleled accuracy of power-aware simulation from the Sigrity solution with the advanced visualization and static timing analysis capabilities of TimingDesigner.”
For more information or a demo of the TimingDesigner 9.4 capabilities, visit us on our website or call 800-813-7494, or contact your local Cadence AE or salesperson.