Allegro FPGA System Planner

FPGA-PCB co-design with automatic rules-driven pin assignment

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FPGA-PCB Co-Design Made Easy

Replace manual, error-prone processes with automatic pin assignment synthesis eliminating physical design iterations while speeding optimum pin assignment.

Device-Accurate FPGA Models

The FPGA Model Library included incorporates pin assignment and electrical rules specified by FPGA device vendors—ensuring vendor-defined electrical usage rules of FPGAs are strictly adhered to.

Integration with PCB and FPGA Design Tools

Generate and read supported FPGA vendors’ pin assignment constraint files, enabling the FPGA designer to evaluate pin assignments against the functional needs of the FPGA.

Improve Routability and Minimize Net Crossovers

A built-in DRC engine incorporates the rules provided by FPGA vendors for pin assignment, reference voltages, and terminations—preventing PCB physical prototype iterations.

Placement-Aware Pin Synthesis

Shorten the time required to create pin assignments for a large number of FPGAs and quickly create DRC accurate FPGA pin assignments.

Interface Definitions

Specify connectivity between components within the FPGA sub-system at a higher level.

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Additional information and details are available in the Allegro FPGA System Planner datasheet.

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Find the version and licensing agreement that best fits your needs and budget.


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Create High-Quality FPGA-Based Systems

View these recommendations for power-supply connections, pin selections and assignments, and other tips and methodologies in this paper from Cadence.

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Shorten ASIC Prototype Time

See how VeriSilicon shortened their FPGA-based ASIC prototype development time by 75% and completed optimal pin assignment in one week.

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ASIC Prototyping Simplified

Allegro® FPGA System Planner offers a simplified and more flexible approach to ASIC Prototyping.

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