OrCAD FPGA System Planner

Optimum, Correct-By-Construction Pin Assignments in a Complete, Scalable Solution.

Request Info

FPGA Rules Driven FPGA-PCB Co-design

Simplify Routing and Reduce Costs

FPGA pin synthesis engine determines optimum connectivity solution to ease routing and avoid the need to for excessive vias / layers to complete interconnect for FPGA based designs.

High-Level Connectivity Specifications

Specify connectivity between components within the FPGA sub-system at a higher level through interface definitions.

Complete FPGA Model Library

Ensure vendor-defined electrical usage rules of the FPGA models are strictly adhered to—ensuring proper function of FPGA designs.

Integrated with FPGA Vendor Data

Ensure vendor-defined electrical usage rules of the FPGA models are strictly adhered to—enabling designers to evaluate pin assignments against the functional needs of the FPGA.

PCB Aware

FPGA pin assignments and connections can be used to quickly generate schematics and ensure FPGA rule-correct pin swapping in the PCB during routing.

Get The Specs

Additional information and details are available in the OrCAD FPGA System Planner datasheet.

Download Datasheet

Get The Price

Find the version and licensing agreement that best fits your needs and budget.

 

Pricing Information

Create High-Quality FPGA-Based Systems

View these recommendations for power-supply connections, pin selections and assignments, and other tips and methodologies in this paper from Cadence.

Read Now

Need to Perform Complicated ASIC Prototyping?

Allegro® FPGA System Planner offers a simplified and more flexible approach to ASIC Prototyping.

Learn About Allegro FPGA System Planner

Need more info?

The EMA Team will be happy to assist you.

Contact Us