OrCAD FPGA System Planner

Optimum, Correct-By-Construction Pin Assignments in a Complete, Scalable Solution.

FPGA Rules Driven FPGA-PCB Co-design

Simplify Routing and Reduce Costs

FPGA pin synthesis engine determines optimum connectivity solution to ease routing and avoid the need to for excessive vias / layers to complete interconnect for FPGA based designs.

High-Level Connectivity Specifications

Specify connectivity between components within the FPGA sub-system at a higher level through interface definitions.

Complete FPGA Model Library

Ensure vendor-defined electrical usage rules of the FPGA models are strictly adhered to—ensuring proper function of FPGA designs.

Integrated with FPGA Vendor Data

Ensure vendor-defined electrical usage rules of the FPGA models are strictly adhered to—enabling designers to evaluate pin assignments against the functional needs of the FPGA.