Allegro/OrCAD/PSpice Version History

Cadence is committed to continuous improvement of the performance of its products, which, in turn,
impacts your productivity. These improvements are driven by your suggestions, technological
innovations, expected or current market changes, and in-house research. Many updates have been included in this release including performance improvements for design rule checks (DRCs), via arrays, daisy chain generator, shapes, placement, and interactive placement.

This release introduces positive masks, an enhancement for mask layer visualization and manufacturability. Traditionally, mask layers are negative, where the visible objects on the canvas represent openings in the mask. The traditional approach requires designers to mentally invert the image to understand the manufactured outcome. Interpreting these negative mask visuals as positive during 3D rendering or manufacturability checks can be counterintuitive and error-prone, adding complexity to the design and review process.

With this new feature, mask layers can be treated as positive, making it easier to visualize and verify mask shapes. A new option, Positive Mask, has been added to the Cross-section Editor. When enabled, a dynamic shape is generated on a new Positive Mask class, representing the mask layer. Openings in this dynamic shape use the same model as dynamic copper shapes, however, voiding is performed using the traditional negative mask pads in padstacks and objects on mask subclasses, which are typically exported for manufacturing.

This update modernizes the way text is managed in PCB designs, aligning the tool with industry-standard applications. You now have the flexibility to choose from a wide range of fonts that reflect personal or corporate branding while also improving the visual clarity and consistency of design documentation. In addition to standard fonts, the Mooretronics font is also supported within layout editors.

The docked Constraint Manager is a new Constraints panel that simplifies the process of assigning and visualizing constraints directly from the Layout Editor user interface. It presents constraints in a graphical format and organizes them under Basic and Advanced modes. Constraints can be controlled at the group level rather than the net level by assigning constraint sets at the net group, net class, and differential pair levels within the Object Hierarchy panel.

The Search panel is a new dockable panel that allows you to instantly query database objects and cross-probe them from the canvas or panel to find information and objects quickly. This provides on-demand content loading to reduce memory usage and improve performance, real-time updates to ensure you have access to the latest information, and custom column filtering to allow columns to be rearranged as needed.

Smart Search is a new search engine that generates predictions based on entered keywords or questions to find the information you need to complete a task directly in the layout. This feature is useful when modifying the design by applying object properties or setting user preferences while working on it.

A new configuration-based solution defines all required data exports and manages export parameters in a single dialog box. It eliminates the need to explore different areas of the layout editor to produce manufacturing exports.

The enhanced pin delay import feature provides auto-detection, column and cell validation, and the ability to adjust column categories and values directly within the dialog box without modifying the source CSV file. The enhanced functionality queries the database to flag missing Reference Designator and Pin Number combinations in the design and allows selective import by deactivating rows and columns as required.

In this release, Cadence continues to expand the capabilities of 3DX Canvas, helping designers visualize their PCB layouts in a highly realistic 3D environment before sending the layouts to manufacturing. 3DX Canvas has been enhanced to selectively display and incrementally add objects to the 3DX Canvas, making the environment far more interactive and efficient. You can now highlight selected objects in the 3DX canvas from the PCB, cross-probe objects, and adjust the 3D view automatically.

OrCAD X PCB Editor has several performance enhancements added included DRCs, import and export of design data, placement and interactive placement, routing and interactive routing, dynamic shapes, padstack refresh, 3D view, and in-design analysis.

The following new SKILL functions have been added:

• axlGetPreselectSet: Returns a list of the currently preselected database objects.
• axlGetPreselectSetCount: Returns the count of the number of objects in the preselection set.
• axlXSectionGetDrillDirection: Returns a symbol indicating the drill direction for the layer pair.
• axlSetRKSPCTolerance: Sets the allowable tolerance for a route keepout based on spacing domain rules.
• axlGetRKSPCTolerance: Returns the route keepout or route keepin-based tolerance value.
• axlDumpDRCModelinXML: Dumps DRCs in a particular category in an XML file.
• axlPulseGetDesignUrl: Returns the Pulse design URL.
• axlGetBends: Returns a list of bend names.
• axlGetBendInnerRadius: Returns the inner radius value for a bend name.
• axlSetBendInnerRadius: Sets the inner radius value for a bend name.
• axlFormIntroDoc: Describes control types and functions for creating interactive forms.
• axlImportDegassingParams: Imports degassing parameters from an Excel file.
• axlImportMetalFillParams: Imports metal fill parameters from an Excel file.
• axlDBChangeText: Modifies the characteristics of a text string in the layout.
• axlDBChangeTextStyle: Modifies an existing text style using the specified text style parameters.
• axlDBGetTextStyleCharacteristics: Returns the characteristics of a text style object.
• axlDBGetTextStyle: Returns the text style information.

The following SKILL functions have been modified:

• axlPadOnLayer: Tests if a pad is present on an etch layer.
• axlCanvasPrintToPDF: Saves the design file in PDF form.
• axlDBControl: Inquires or sets the value of a special database control.
• axlTriggerSet: Allows registering interest in events that occur in the database.
• axlParamShapeDoc: Supports access to the dynamic, static, and layer parameter records.
• axlDBCreateText: Creates a text string.
• axlDBCreatePin: Adds a pin.
• cmxlExportFile: Exports Constraint Manager object information to a file.
• cmxlImportFile: Imports a file to update a Constraint Manager object.
• cmxlFindOrCreateQBR: Queries a database object and returns an object if it exists or creates it if it does not.

The Reports panel is a new dockable panel that automatically loads selected Quick Reports for easier review and canvas navigation. This panel eliminates the need to manage a separate floating report viewer for the Shape Islands Report, Unassigned Shapes Report, Missing Teardrops Report, Missing Tapers Report, and the Dangling Traces, Vias, and Antenna report.

25.1 introduces a new dialog box, Differential Pair Automatic Setup, which provides a unified solution for generating differential pairs. This dialog box combines all unique features in the existing solutions available within and outside the Constraint Manager and simplifies the process of generating differential pairs.

The metal density scan command, used to perform metal density analysis of design layers, is enhanced for performance. The command also provides additional metal density checks and options to meet manufacturing requirements such as minimum/maximum metal density across layers and metal density difference between two layers.

You can now run thermal analysis directly in the familiar Allegro X Layout Editor framework, which significantly optimizes the design process and compresses the overall design cycle.

3DX canvas has been enhanced with all the functionalities found in the 3D Canvas and unrestricted design size. 3DX canvas can now be navigated with the keyboard using the arrow keys.

You can now use the model mapper tab to map 3D models to footprints, devices, or mechanical components. Import and export functionality allows you to export a mapping file of the existing components and their associated mapped models and import the file after editing to update the components.

Export 3DX canvas designs into the OpenUSD (Universal Scene Description) format that is needed to import into the NVIDIA Omniverse platform.

Frozen dynamic shapes can be selected to resolve all dynamic voiding DRC Errors using the Update Shape command, which updates dynamic voids across the entire shape. Additional commands have been added to delete any dynamic voids inside a frozen dynamic shape, select dynamic voids, and define a void area for update.

To void shapes underneath an object (Example: to avoid coupling noise from adjacent shapes, establish impedance reference several layers down, or remove unwanted return path references), the new void adjacent layers command allows you to select objects on the canvas for which adjacent voids will be automatically generated.

Enter single-ended and differential impedance requirements directly in the cross-section editor for automatic generation of the appropriate physical constraint set for net assignment in the constraint manager.

The Quickviews list in the visibility panel lists all placement layers in a design for quick display, with Component Reference Designators contained inside the component boundary without the need to display additional layers. This new option displays the Top and Bottom placement layers by default with the additional entries for Embedded component and Zone Placement Layers added dynamically.

Objects that can display embedded names is expanded to avoid extensive queries or the display of special layer text that may not always be readable in layout.

• Net Name Labels support Cline, shape, and pins also expanded to support vias
• Drill labels are now expanded to support Thru Via Drills while maintaining the current BB Via/Microvia Drills
• Embedded Component Pin Number display is also added to eliminate the need of displaying the Pin number text.

When routing differential pairs through a dense area, the space transition area has been improved to no longer require excessive lead-ins which results in DRC errors requiring manual cleanup. Improvements have been made to leverage the differential pair trace width and space as well as the pad geometry to calculate the appropriate pad entry that produces DRC-free and manufacturable results.

The new custom smooth option, Allow Electrical DRCs, temporarily ignores electrical constraint DRC errors so that completed routing can be optimized to the shortest, cleanest path and is ready for tuning.

The Delay Tune feature has been enhanced to contour each bump individually to surrounding obstacles with a single drag window, without the need to extend each bump individually using slide, except for final tweaks only to bring the route into spec.

Ignore No Connect (NC) nets by setting a new net property (NC_IGNORE) along with the new user preference (disable_ncnet_count_display). Nets with the NC_Ignore property are not counted in the unrouted nets/unrouted connections count and Quick Reports – Unconnected Pin Report.

Default film record automation is replaced with configuration-based film categories to intelligently generate film records.

• Layer combinations for external/internal conductor layers or planes based on cross section, silkscreen, solder mask, solder paste, and other design/company-specific films
• Global and film category-based film options, such as PDF sequence, undefined line width, domain classification, and IPC-2581 Layer Type.
• Built-in based level configuration is provided with the ability to save user/company specific configuration including support for saving configuration in the library for reuse with other designs.

New Acid Trap check, minimum angle with convex checks, builds upon the existing minimum angle acid trap check, which only find and verifies concave situations. The new check also finds and verifies convex situations for clines and static shapes and combinations of these two design objects as they relate to pads and vias.

Two new DRC-related checks minimize signal integrity impacts early in the design process without solely relying on backdrill to reduce via stubs on high-speed interfaces. These checks can also be used to validate the design during final sign-off before release to manufacturing.

• Pre-Backdrill Awareness (Stub Reduction): Validate routed interconnect stubs leveraging the existing backdrill max PTH stub value used by backdrill to flag vias that violate stub requirements. Optimize routing to eliminate stub, reduce the stub by introducing blind/buried vias, or use backdrill to mechanically drill the stub away.
• Layer Transition Reduction: Analyze routed interconnects to determine the number of routed layer transitions on a particular net. The maximum value is used to determine the number of permissible internal routing connections from source to destination excluding surface routing and the first internal routing layer.

Use a new check to calculate the root sum squared (RSS) length of horizontal and vertical routing, which reports a DRC error when it exceeds an acceptable threshold.

A new check is available that counts the number of times a differential pair is routed between two vias of another differential pair, using controls to check for combinations of vias, pins, or vias and pins. There is also additional control to ignore certain low-speed differential pairs, enabling routing between vias.

Ensure the internal markup and comments are not exposed to external resources when you send the designs out to third-party vendors. Quickly remove comments and markup from the database and archive them to a local file.

3DX canvas has been improved to include cutting planes, material colors, transparency control for all 3D objects, 3D DRC display options, and measuring in 3D. Updates include:

• Cut the 3D view of the PCB in any combination of the X, Y, and Z axes to get the exact view required.
• Control the color of all manufacturing materials to produce photo realistic 3D images
• Increase detail and control of visibility and transparency for detailed 3D views
• Customization of the 3DX canvas with visibility and preferences
• Control the display of 3D spacing violations to see space overlaps and space needed.
• Measure the 3D air gap

DFA alignment can be used for group placement by selecting multiple components. Set the DFA_PAUSE_LEVEL to 4 in the User Preferences Editor.

When using the legacy DFA table you will receive an option to move to the new DesignTrue DFA table.

A new check has been added to check the pastemask against a component body (PLACE_BOUND or DFA_BOUND).

Switch the basic component overlap and height checks on the 2D canvas to utilize the DFA Bound shapes instead of the traditional place bound shapes.

Configure your layout editor environment in a local language by setting Use local language under UI- Language & Fonts in User Preferences.

Copy and paste pad geometries within the same tab or between the design and mask layer tabs to save time during padstack creation.

Configure the plot setup for generic operating system-related page setup in the preview window along with other advanced options.

Customize the timing meter colors. Colors are no longer limited to the defaults of Red (Error), Yellow (Warning) and Green (Pass) conditions.

High-Speed interfaces require special treatment to avoid signal integrity issues under components and component pins by generating openings in adjacent planes while preventing routing from running through these openings in the planes. Now you can automatically generate adjacent keepouts by tagging certain components, pins and nets that require this treatment.

Adjacent keepout definitions can be managed on the schematic or layout and can be transferred back and forth using the Front to Back Flow.

Manage and edit the properties in the layout editor using Properties or inside the Constraint Manager.

Manage net properties in the properties section of Constraint Manager. Use the electrical properties worksheet to enable nets or groups of nets that should have dynamic adjacent keepouts generated.

Automatically generated keepouts are associated with component/pin and move/mirror along with the component, including during zone and embedded placement.

A new Query Based Rules workbook is available in the same net spacing domain and drives spacing rules between vias padstacks in the design. This allows a high level of flexibility in developing specific Same Net Via to Via rules based on groups of Vias, trace connected or not trace connected (stitch vias).

Sometimes you need to reduce trace width when routing through BGA pin fields, which results in a higher impedance causing signal integrity issues. Enhancing traces with small trapezoidal copper shapes (routing tabs) lowers impedance to avoid these impedance discontinuities. Tabbed routing has been enhanced to improve net selection and analysis. The Xnet dialog box has advanced filtering and hierarchical group selection to ensure all nets are selected for analysis. Improved analysis dialog box includes net groups and differential pair membership for each row allowing a more focused review by sorting results. Additional options are available to verify tab counts between net group members or between the nets within a differential pair.

Cadence Doc Assistant presents help content as individual easy-to-read topics and has improved the speed and relevance of search capabilities.

Facilitate a collaborative design review environment with the ability to markup and comment design feedback directly in the PCB canvas. Markups are stored in the design database, streamlining the design review process.

Define secondary drill definitions on either the primary or secondary side.

Expanded the capability of microvia drill support beyond circle and square-plated holes to include microvia slot. This allows rectangular or oval-plated slots while following standard microvia constraints in the design.

Drilled hole fields for circle and square holes as well as round slot fields for rectangle and oval shot holes have been added for accurate unit-controlled values of the drill hole size before plating and tolerances.

Pitch values for rows and columns can now be defined to calculate the spacing automatically for a multi-drill.

When dynamic shapes need to remain constant to protect critically circuitry and maintain design intent, suspend or freeze dynamic voiding instead of converting to static shapes. Once frozen, new objects entering a shape will not void and will generate a DRC error.

Components placed in a zone with some of the pins protruding into another zone can cause buried or floating pins. Easily check to verify that all pin pads of a component exist on the same placement layer.

Designate stackup differences in particular areas of your rigid-flex designs by defining one zone inside another for scenarios where one shape needs to be surrounded by another.

Zone modifications can now be performed without activating Shape Edit Application Mode.

Define the fill-in material for multi-layer PCBs to account for the different dielectric constants that affect the electrical characteristics of conductors running across the dielectric​.

Define dimension parameters to apply a line width globally for all dimensions.

Define the net during Z-copy to copy etch shapes to other layers. Incorporate a subclass wildcard to copy the shape to multiple layers.

A new delete option will remove routing from the previous module for components that are part of another module.

Reuse device files and component definitions that are currently in the design when loading an updated netlist.

New net short properties report is available to easily find all the objects in the design with the Net short property to verify the nets being shorted.

New high-voltage constraint checks to verify creepage and clearance rules. Design Rule check system recognizes non-plated slots between two high-voltage objects and recalculates creepage and clearance. Creepage and clearance vision provides graphical feedback with color-coding directly on the canvas for efficient analysis.

Quickly generate power planes for a section of the design of the entire design based on pin placement, boundary, or design outline. Review power plane escape and adjust placement or constraints to improve power connections.

A new routing tab utilizing complex shapes that follow serpentine pattern contouring to pins and vias allows you to maximize tab size and reduce impedance when routing through CPU pin-fields.

Automatic mapping and fine-tuning of the x, y, and z placement provides efficient methods for mapping 3D models to the footprint directly in the library.

Export the complete 3D representation of the entire design or individual objects as STEP, IGES, ACIS or a PDF.

When reusing structures multiple times, easily update one instance and push the changes to all instances.

Easily make changes to a dimension without having to delete and regenerate it.

Easily locate stacked vias and flag them with DRC markers in restricted areas.

Enhancements include better performance on designs with a large number of DRCs, faster update to smooth, better move performance, better performance for shape parameter per layer override, capping of command window messages, and faster DRC checking on designs with negative layers.

GPU support now includes modern discrete or integrated GPUs from Intel and AMD. Enhancements to NVIDIA GPUs include performance gain in panning and zooming and augmented quality of display.

Easily specify a scaling factor to normalize forms that are partially cut off due to display scaling in devices with 4k or higher resolution.

A non-analysis version of Topology Workbench for constraint capture is now included.

Easily convert objects and create or replace an object with a padstack directly on the canvas.

Faster structure creation for parameterized high-speed structures by leveraging information from other areas and extracting information from selected differential pair transitions.

Replace via with structure has been updated to accept structures that do not contain pad entry or exit traces maintaining current routing and delay matching.

Leverage GPU in Allegro Layout Editors to improve response time during panning and zooming, toggling layers, and render quality.

Navigation improvements for the DRC Browser and the ability to waive DRC by group select.

New analysis mode option to enable line based checks for fillets.

Improved shape performance for copper pours and editing smooth shapes. Fast mode replaces rough mode and drastically improves the performance during active etch editing including slide, add connect, move, and more. Improved performance in shape voiding quality including crosshatch shape fill improvement, fillet void quality improvement, and trim void improvement.

Isometric view has been added for the bottom side of the board. Other updates include realistic plating thickness, increased model realism, and secondary model support.

Dynamic shapes are automatically converted to static shapes to ensure consistent voiding. Modules applied to the design remain locked to avoid accidental modification. Addition of copper planes, constraint regions and text notes within the module file. Quickly swap a placed reuse module with a different variant in one or multiple locations.

Multi-pin scribble support when routing allows you to digitize a path through a pin field to make connections. Recognizes the same net pins and snaps to center while routing.

Improvements include DFF Mask Rule Additions (via and SMD pad overlapping soldermasks), updated calculations for aspect ratio and line-based checks for fillets. DFM Wizard Enhancements to support DFF and DFA templates for copper features, copper spacing, DFA spacing, and component leads. Navigation improvements for the DRC Browser and the ability to waive DRC by group select. Component Lead geometry can now be displayed with control in the visibility pane.

Updated to include shape void and plane edge checks to verify trace coverage by identifying overhang conditions and ensuring appropriate plane overlap is present.

Easily enter parameters by selecting differential pair vias on the canvas to build a replacement structure for pre-existing routing. Includes five pre-defined geometries: rings, owl, oval, rectangle, and goggles.

Improvements have been made to via structure support, in-session component placement usability and database sharing usability.

Align vias horizontally or vertically to improve routing and plane coverage.

Launch PCB Editor viewer from the project hierarchy.

3D mapper now a part of 3D canvas, replacing Allegro (2D) menu. Simplified use model and GUI enhancements. Improved accuracy of collision detection and distance measurements. Additional support for mapping native CAD models (Parasolid, Siemens NX, CREO, SOLIDWORKS).

Additional support for rigid flex (bend detail and stack-up profiles), Countersink/counterbore, square drill features, net shorts, and impedance specifications and nets.

Bend sequence ordering, Geometry use identification, primary pin identification, and time stamps.

DesignTrue DFM Enhancements including Enable/Disable Switch for on-line DFM checks, Global Manufacturing Tolerance and Tented Via List Enhancements (top tented via list and Bottom via list). DesignTrue DFM Rule Aggregator combines DFM rules and produces a set of rules with the common denominator based on the most conservative values.

Now Symphony clients can place components directly from the placement list onto the canvas transferring the symbol data to the Symphony server database with In-session component placement.

Enhancements include improved usability and import of CSV Constraint Tables and XML Constraint Data Set.

This prototype solution generates high-speed structures based on parameters.

Setup and manage your fabrication panels directly within PCB Editor.

You can now use the new Design Setup Workflow to prepare for analysis by setting up your design for the different checks. You can set up cross-section, DC nets, components, Xnets, and differential pairs. You can then save the design with the changes. As with all other workflows, you can access this workflow from the Analysis Workflows pane (Analyze – Workflow Manager).

In this release, performance improvements are a top priority resulting in greatly improved launch times and reduced memory usage.

You will see the re-designed filter dialog. With this redesigned dialog. You have the choice of selecting what layers to visualize in 3D Canvas – All Layers or Outer Layers only, and what objects you wish to bring into the 3D Canvas. You can now visualize much larger designs in 3D Canvas by eliminating memory straining objects.

A new pane has been added to 3D Canvas – the Nets pane. Prior to this release, nets were visualized on the 3D Canvas, but no underlying information regarding nets were imported. With this release, net information (names, type, properties, and so on) are also imported into 3D Canvas and the new Nets pane allows you to control how to visualize the nets in 3D Canvas. You can select All Nets (the default view) and any other groups of nets contained in a design.

Prior to this release, components selected on the 2D side or selected in 3D Canvas were shown in 3D Canvas as selected (red). With this release, two new highlighting choices are available – Dim and Vanish. With the Dim option, selected objects still appear on the canvas as red while the remainder of the elements are dimmed. With the Vanish option, selected objects appear on the canvas as red while the remainder of the elements disappear.

Allegro® In-Design Analysis environment blends the best of Allegro® and Sigrity™ technologies to provide analysis and checking capability entirely within the PCB Editor framework for Impedance, Coupling, Crosstalk, Reflection, Return Path and IR Drop. PowerTree files are no longer needed for IR Drop analysis with the ability to define VRM’s directly within the design workflow.

Support for new types of constraints such as a new table to define Routing Sections within a net or XNet for assignment of Physical, Spacing, and Electrical constraints in an ObjectRule Table.

Version control features are available as an unsupported prototype within Allegro® PCB Editor. Native version control allows you to capture versioned snapshots of a design throughout the design process and provides an easy way for you to reference or revert to a previous version of the design.

Package Templates have been re-organized for easier selection, Rule Editing has been simplified, and manual footprint creation has been expanded with improved Boolean operations involving path and area geometries.

The new rules manage the number of microvias stacked over a core via, and alignment tolerance from center-to-center of microvia to core via and microvia to microvia. These checks help avoid microvia barrel cracking and via delamination during the entire fabrication process.

Custom icon support for toolbars allows users to add user-selected icons to commands when customizing toolbars. In the Find by Query dialog, a new attribute Width has been added for Lines.