Resource Library
Posted on Nov 11, 2016
Sigrity technologists guide you step by step on how to use the Sigrity Finite Difference Time Domain (FDTD) simulator to accurately predict the impact of simultaneous switching noise (SSN) in a system context. A PCB layout is directly connected to a system topology without having to perform an S-parameter extraction. This “FDTD-direct” methodology overcomes the challenge faced by SI engineers who fear accuracy could be compromised when converting an S-parameter to a simplified broadband spice model.
Posted on Oct 7, 2016
Sigrity technologists guide you step by step on how to setup a leadframe package design for accurate extraction using the 3D quasi-static solver engine. Accurate RLC extraction is performed on a leadframe design from the same environment used to model multi-layer packages with other solver engines. Design productivity is improved by enabling a common environment to model leadframe, flip-chip, and wirebond IC Packages.
Posted on Sep 9, 2016
Allegro Sigrity SI Base and Power-Aware SI Option from Cadence are demonstrated. Sigrity technologists guide you step by step on how to utilize power-aware electric rule checks to confidently fast track the sign off process for your PCB designs.
Posted on Jun 1, 2016
Optimizing IR drop, OneStor Solutions group, CSES, Bangalore, Goutham, Shashi & Subbu
Posted on Nov 10, 2015
Learn how Sirius XM was able to easily adopt Cadence Sigrity to help them achieve first pass success