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For the past 15 years or so, routing high-speed interfaces handling 5Gbps or higher have become more common in many electrical designs. Transitioning high-frequency signals between layers can greatly affect signal integrity when a portion of plated through-hole (PTH) is left unused, forming an electrical stub. In general, these stubs are a source of impedance discontinuities and signal reflections, which become more critical as data rates increase.

I can read your minds as you digest the features and benefits of our Allegro 17.2-2016 Release. “Oh no, what have they done now to disrupt my environment?” If you have been an Allegro user for many years, you know what I’m talking about. Dot Zero releases as we call them are our chance to make database / schema changes that result in some level of migration disruption. 17.2 effectively is your dot zero release as it combines the content from the Early Access Program 17.0 software with that of 17.2.

When (not if) change happens or scope creeps... the PCB design team is always on the critical path. You can answer this schedule challenge by dynamically scaling resources with the new Concurrent Team Design capabilities in the Allegro 17.2 2016 Release.

The OrCAD/Allegro 17.2-2016 release, the largest in the past 10 years, became available in late April 2016. Since 17.2-2016 includes a database change that usually happens with a dot zero release, many of you may be wondering when the right time to migrate to this new release is.