Posted on May 5, 2017
Assuring power integrity of a PCB requires the contributions of multiple design team members. Traditionally, such an effort has involved a time-consuming process for a back-end-focused expert at the front end of a design. This paper examines a collaborative team-based approach that makes more efficient use of resources and provides more impact at critical points in the design process.
Posted on Sep 30, 2016
Let’s start by clarifying some terms. DFM is short for “Design for Manufacturability”. It is the process of arranging a PCB layout topology to mitigate problems that could be encountered during the PCB fabrication and assembly processes required to manufacture an electronic system.
Posted on Jul 14, 2016
The Cadence® PSpice® A/D release 17.2-2016 offers a comprehensive feature set to address design challenges in IoT sensors, controllers, and actuators. With system simulation and modeling technology that enables a unified design environment for mixed-signal design, PSpice A/D can help you deliver a high-quality product within your time-to-market window.
Posted on Jun 20, 2016
Flexible PCBs (flex/rigid-flex) make it possible to create a variety of products that require small form factors and light weight, such as wearable, mobile, military, and medical devices. As flexible PCB fabrication technology has matured in response to demands for smaller, lighter products, new design challenges have emerged. This paper discusses some of the key challenges to address and also introduces a new PCB design approach that enhances productivity through in-design inter-layer checks required to ensure correct-by-construction design.
Posted on Apr 18, 2016
Learn how the unique Allegro TimingVision Environment speeds up timing closure of high-speed PCB interfaces
Posted on Feb 23, 2016
Learn how PSpice allow you to perform early system level analysis of your designs.
Posted on Sep 28, 2015
Integrating EMA TimingDesigner with Xilinx and Altera Development Systems.