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Posted on Sep 25, 2018
Set aliases to nets and buses, which will be very useful for the layout process.
Posted on Sep 25, 2018
Place wires to connect components in your design, place and connect buses and learn the basics of autowire.
Posted on Sep 25, 2018
Search and place parts to the design from Cadence default libraries and the library you have created.
Posted on Sep 25, 2018
Set up your library by adding parts from an existing Capture default library or create a new part from scratch.; You can also subscribe to Ultra Librarian to download from millions of pre-built components.
Posted on Sep 25, 2018
Create a new schematic project in OrCAD Capture, set preferences for the schematic design canvas, add a title block and create a new library for the design.
Posted on Sep 25, 2018
Quick video showing you how to use this OrCAD tutorial.
Posted on Sep 25, 2018
Sigrity technologists guide you step by step on how to apply an ESD gun model to simulate an ESD event on a printed circuit board.
Posted on Sep 25, 2018
Learn how complex structures such as via arrays can be designed, optimized and updated in an integrated Allegro-Sigrity design methodology without redrawing via structures.
Posted on Sep 25, 2018
Sigrity technologists guide you step by step on how to automatically set-up PDN simulation from schematics, collect and verify components models, and perform analysis as early as possible. Your PCB design team will learn how they can share DC analysis responsibility throughout the design cycle by utilizing PowerTree™ technology.
Posted on Sep 25, 2018
Sigrity technologist Brad Brim guides you step by step on how to perform full-wave 3D extraction on the right slice of a PCB or IC Package design.

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