DDR4 Measurement Report

- Data Bus, 2.4Gbps, Write

Generated by Topology Workbench, Cadence Design Systems Inc.,
Sunday, 19 February 2023

Useful Links:

Cadence website: http://www.cadence.com
DDR4 SDRAM Specification: http://www.jedec.org/sites/default/files/docs/JESD79-4.pdf

1 General Information
2 Simulation Setup
- 2.1 Rank Definition
- 2.2 Model Selection and Stimulus
  - 2.2.1 Controller
  - 2.2.2 Memory
- 2.3 Signal Connectivity
- 2.4 Simulation Description
3 DDR Measurement Setup
- 3.1 AC and DC Logic Input Levels
- 3.2 Specs
  - 3.2.1 Data Bus Write
4 Results
- 4.1 Data Bus Write
  - 4.1.1 Waveform Quality Report
    - 4.1.1.1 Worst Case Summary
  - 4.1.2 DQ Mask Report
    - 4.1.2.1 Worst Case Summary
  - 4.1.3 BER Report
    - 4.1.3.1 Worst Case Summary
  - 4.1.4 Delay Report
    - 4.1.4.1 Worst Case Summary
5 Appendix
- 5.1 JEDEC DDR Measurement Definitions
- 5.2 Description of Abbreviations

1 General Information ^

Topology File: C:\Users\avira\Desktop\Demo files\4. SPBS\spbs\spbs_1c_ddr4.topx
Controller IBIS File: C:\Users\avira\Desktop\Demo files\4. SPBS\spbs\ddr_pba_ex.ibs
Memory IBIS File: C:\Users\avira\Desktop\Demo files\4. SPBS\spbs\ddr_pba_ex.ibs
Block 'TuningBlock' Model File: C:\Users\avira\Desktop\Demo files\4. SPBS\spbs\strobe_tuning_traces_All_TL.sp
Circuit Simulator: SPDSIM
Topology:

2 Simulation Setup ^

2.1 Rank Definition ^

Rank Name	Memory Blocks
Rank1	Mem

2.2 Model Selection and Stimulus ^

2.2.1 Controller ^

OnDie Parasitics: None; Package Parasitics: Pin RLC.
Bus Group	Signal	Pin	Stimulus Pattern	Stimulus Offset (ns)	Transmit IO Model	Status
DataL	DQ0	87	10001101011100011001...	0.5T	DDR4_DQ34N48P_NO_ODT	Signal
	DQ1	80	10001101011100011001...	0.5T	DDR4_DQ34N48P_NO_ODT	Signal
	DQ2	85	10001101011100011001...	0.5T	DDR4_DQ34N48P_NO_ODT	Signal
	DQ3	82	10001101011100011001...	0.5T	DDR4_DQ34N48P_NO_ODT	Signal
	DQ4	62	10001101011100011001...	0.5T	DDR4_DQ34N48P_NO_ODT	Signal
	DQ5	69	10001101011100011001...	0.5T	DDR4_DQ34N48P_NO_ODT	Signal
	DQ6	64	10001101011100011001...	0.5T	DDR4_DQ34N48P_NO_ODT	Signal
	DQ7	67	10001101011100011001...	0.5T	DDR4_DQ34N48P_NO_ODT	Signal
	LDQS	77	10..	0.75T	DDR4_DQS34N48P_NO_ODT	Timing Ref
	LDQS#	75	01..	0.75T	DDR4_DQS34N48P_NO_ODT	Timing Ref
DataU	DQ8	94	10101010..	0.5T	DDR3_DQ34_NO_ODT	Not Connected
	DQ9	101	10101010..	0.5T	DDR3_DQ34_NO_ODT	Not Connected
	DQ10	96	10101010..	0.5T	DDR3_DQ34_NO_ODT	Not Connected
	DQ11	99	10101010..	0.5T	DDR3_DQ34_NO_ODT	Not Connected
	DQ12	118	10101010..	0.5T	DDR3_DQ34_NO_ODT	Not Connected
	DQ13	111	10101010..	0.5T	DDR3_DQ34_NO_ODT	Not Connected
	DQ14	116	10101010..	0.5T	DDR3_DQ34_NO_ODT	Not Connected
	DQ15	113	10101010..	0.5T	DDR3_DQ34_NO_ODT	Not Connected
	UDQS	104	10..	0.75T	DDR3_DQS34_NO_ODT	Not Connected
	UDQS#	106	01..	0.75T	DDR3_DQS34_NO_ODT	Not Connected

2.2.2 Memory ^

OnDie Parasitics: None; Package Parasitics: Pin RLC.
Bus Group	Signal	Pin	Receive IO Model	Standby IO Model	Status
DataL	DQ0	E3	DDR4_DQ34N48P_ODT	DDR3_DQ34_NO_ODT	Signal
	DQ1	F7	DDR4_DQ34N48P_ODT	DDR3_DQ34_NO_ODT	Signal
	DQ2	F2	DDR4_DQ34N48P_ODT	DDR3_DQ34_NO_ODT	Signal
	DQ3	F8	DDR4_DQ34N48P_ODT	DDR3_DQ34_NO_ODT	Signal
	DQ4	H3	DDR4_DQ34N48P_ODT	DDR3_DQ34_NO_ODT	Signal
	DQ5	H8	DDR4_DQ34N48P_ODT	DDR3_DQ34_NO_ODT	Signal
	DQ6	G2	DDR4_DQ34N48P_ODT	DDR3_DQ34_NO_ODT	Signal
	DQ7	H7	DDR4_DQ34N48P_ODT	DDR3_DQ34_NO_ODT	Signal
	LDQS	F3	DDR4_DQS34N48P_ODT	DDR3_DQS34_NO_ODT	Timing Ref
	LDQS#	G3	DDR4_DQS34N48P_ODT	DDR3_DQS34_NO_ODT	Timing Ref
DataU	DQ8	D7	DDR3_DQ34_NO_ODT	DDR3_DQ34_NO_ODT	Not Connected
	DQ9	C3	DDR3_DQ34_NO_ODT	DDR3_DQ34_NO_ODT	Not Connected
	DQ10	C8	DDR3_DQ34_NO_ODT	DDR3_DQ34_NO_ODT	Not Connected
	DQ11	C2	DDR3_DQ34_NO_ODT	DDR3_DQ34_NO_ODT	Not Connected
	DQ12	A7	DDR3_DQ34_NO_ODT	DDR3_DQ34_NO_ODT	Not Connected
	DQ13	A2	DDR3_DQ34_NO_ODT	DDR3_DQ34_NO_ODT	Not Connected
	DQ14	B8	DDR3_DQ34_NO_ODT	DDR3_DQ34_NO_ODT	Not Connected
	DQ15	A3	DDR3_DQ34_NO_ODT	DDR3_DQ34_NO_ODT	Not Connected
	UDQS	C7	DDR3_DQS34_NO_ODT	DDR3_DQS34_NO_ODT	Not Connected
	UDQS#	B7	DDR3_DQS34_NO_ODT	DDR3_DQS34_NO_ODT	Not Connected

2.3 Signal Connectivity ^

Controller Signal	Controller Pin	Memory Signal	Memory Pin	Average Magnitude
Ctrl::DQ0	Ctrl::87	Mem::DQ0	Mem::E3	0.910327
Ctrl::DQ1	Ctrl::80	Mem::DQ1	Mem::F7	0.910326
Ctrl::DQ2	Ctrl::85	Mem::DQ2	Mem::F2	0.910326
Ctrl::DQ3	Ctrl::82	Mem::DQ3	Mem::F8	0.910326
Ctrl::DQ4	Ctrl::62	Mem::DQ4	Mem::H3	0.910326
Ctrl::DQ5	Ctrl::69	Mem::DQ5	Mem::H8	0.910326
Ctrl::DQ6	Ctrl::64	Mem::DQ6	Mem::G2	0.910326
Ctrl::DQ7	Ctrl::67	Mem::DQ7	Mem::H7	0.910326
Ctrl::LDQS	Ctrl::77	Mem::LDQS	Mem::F3	0.853127
Ctrl::LDQS#	Ctrl::75	Mem::LDQS#	Mem::G3	0.853127

2.4 Simulation Description ^

Iteration #	Result Folder	TuningBlock>prop_data
1	history\3\DDR4-SPBS-SWEEPSIM1\Data_Write_Typ_Typ_1\DiePad	300p
2	history\3\DDR4-SPBS-SWEEPSIM1\Data_Write_Typ_Typ_2\DiePad	500p
3	history\3\DDR4-SPBS-SWEEPSIM1\Data_Write_Typ_Typ_3\DiePad	700p

3 DDR Measurement Setup ^

3.1 AC and DC Logic Input Levels ^

Single-Ended Signals (V)

Iteration#	Receiver	Corner	VIH(ac) min	VIL(ac) max	VIH(dc) min	VIL(dc) max	Vcent_DQ	VDDQ
1	Mem	Typ	0.832	0.632	0.807	0.657	0.732	1.5
2	Mem	Typ	0.82	0.62	0.795	0.645	0.72	1.5
3	Mem	Typ	0.832	0.632	0.807	0.657	0.732	1.5

Differential Signals (V)

Iteration #	Corner	VIHdiff(ac) min	VILdiff(ac) max	VIHdiff(dc) min	VILdiff(dc) max
1	Typ	0.2	-0.2	0.15	-0.15
2	Typ	0.2	-0.2	0.15	-0.15
3	Typ	0.2	-0.2	0.15	-0.15

3.2 Specs ^

3.2.1 Data Bus Write ^

	Symbol	Min	Max	Unit	Parameter
DQ Mask	Vref	0.60	0.92	VDDQ	Vref range
	Vref_step	0.008	-	VDDQ	Min Vref stepsize
	Vref_set_tol	0.0015	-	VDDQ	Min Vref set tolerance
	VdIVW	130	-	mV	Rx Mask voltage pk-pk
	TdIVW	0.2	-	UI	Rx timing window
	tDQS2DQ	-0.17	0.17	UI	Rx Mask DQS to DQ offset
	tDQ2DQ	-	0.105	UI	Rx Mask DQ to DQ offset
	VIHL_AC	160	-	mV	DQ AC input swing pk-pk
	TdIPW	0.58	-	UI	DQ input pulse width
	SlewRate_Mask	1.0	9	V/ns	SlewRate mask range
	SlewRate_AC_Swing	0.2	9	V/ns	SlewRate AC swing range

4 Results ^

Iteration 1: C:\Users\avira\Desktop\Demo files Feb\Part-10 Demo Files\spbs\history\3\DDR4-SPBS-SWEEPSIM1\Data_Write_Typ_Typ_1\DiePad
Iteration 2: C:\Users\avira\Desktop\Demo files Feb\Part-10 Demo Files\spbs\history\3\DDR4-SPBS-SWEEPSIM1\Data_Write_Typ_Typ_2\DiePad
Iteration 3: C:\Users\avira\Desktop\Demo files Feb\Part-10 Demo Files\spbs\history\3\DDR4-SPBS-SWEEPSIM1\Data_Write_Typ_Typ_3\DiePad

Measurement	Max Overshoot (mV)	Max OvershootArea (V-ns)	Max Undershoot (mV)	Max UndershootArea (V-ns)	Min RBack_marginH (mV)	Min RBack_marginL (mV)	Max Power_Ripple (mVp-p)	Max Tx_Power_Ripple (mVp-p)
Worst Value					329.549	285.692
Iteration					1	2
Bus Group					DataL	DataL
Rx Signal (Waveform)					DQ5	DQ5
Cycle					21	16

4.1.2 DQ Mask Report ^

4.1.2.1 Worst Case Summary ^

Measurement

DQ Compliance Mask

Min
Jitter_margin (ps)

Min
Noise_margin (mV)

Min
VIHL_AC (mV)

Min
TdIPW (ps)

Min
tDQS2DQ (ps)

Max
tDQS2DQ (ps)

|Max|
tDQS2DQ_BC (ps)

Max
tDQ2DQ (ps)

Min
SlewRate_Mask (V/ns)

Max
SlewRate_Mask (V/ns)

Min
SlewRate_AC_Swing (V/ns)

Max
SlewRate_AC_Swing (V/ns)

Worst Value

Pass

96.4797

217.972

733.156

390.85

-64.1784

161.093

3.39509

6.79019

2.87216

3.64248

2.8642

3.63385

Iteration

Bus Group

DataL

Rx Signal

4.1.3 BER Report ^

4.1.3.1 Worst Case Summary ^

Measurement	Min BER Eye Width (UI)	Min BER Eye Height (mV)	Min Eye Contour Height (mV)	Max Eye Contour Jitter (UI)	Max Eye Contour NJN	Min COM (dB)	Min SNR
Worst Value	0.76	708	0.5	742	0.5	22.56	0
Iteration	1	3	1	3	1	1	2
Bus Group	DataL	DataL	DataL	DataL	DataL	DataL	DataL
Rx Signal	DQ2	DQ4	DQ0	DQ2	DQ1	DQ0	DQ7
Iteration	1		1	3	1	1	3
Bus Group	DataL		DataL	DataL	DataL	DataL	DataL
Rx Signal	DQ3		DQ1	DQ3	DQ4	DQ1	DQ0
Iteration	1		1	3	1	1	3
Bus Group	DataL		DataL	DataL	DataL	DataL	DataL
Rx Signal	DQ5		DQ2	DQ5	DQ5	DQ4	DQ1
Iteration	1		1	3		1	3
Bus Group	DataL		DataL	DataL		DataL	DataL
Rx Signal	DQ6		DQ3	DQ6		DQ7	DQ4
Iteration	2		1			3	3
Bus Group	DataL		DataL			DataL	DataL
Rx Signal	DQ0		DQ4			DQ0	DQ5
Iteration	2		1			3
Bus Group	DataL		DataL			DataL
Rx Signal	DQ1		DQ5			DQ1
Iteration	2		1			3
Bus Group	DataL		DataL			DataL
Rx Signal	DQ4		DQ6			DQ2
Iteration	2		1			3
Bus Group	DataL		DataL			DataL
Rx Signal	DQ7		DQ7			DQ3
Iteration	3		2			3
Bus Group	DataL		DataL			DataL
Rx Signal	DQ2		DQ0			DQ4
Iteration	3		2			3
Bus Group	DataL		DataL			DataL
Rx Signal	DQ3		DQ1			DQ5
Iteration	3		2			3
Bus Group	DataL		DataL			DataL
Rx Signal	DQ6		DQ2			DQ6
Iteration			2			3
Bus Group			DataL			DataL
Rx Signal			DQ3			DQ7
Iteration			2
Bus Group			DataL
Rx Signal			DQ4
Iteration			2
Bus Group			DataL
Rx Signal			DQ5
Iteration			2
Bus Group			DataL
Rx Signal			DQ6
Iteration			2
Bus Group			DataL
Rx Signal			DQ7
Iteration			3
Bus Group			DataL
Rx Signal			DQ0
Iteration			3
Bus Group			DataL
Rx Signal			DQ1
Iteration			3
Bus Group			DataL
Rx Signal			DQ2
Iteration			3
Bus Group			DataL
Rx Signal			DQ3
Iteration			3
Bus Group			DataL
Rx Signal			DQ4
Iteration			3
Bus Group			DataL
Rx Signal			DQ5
Iteration			3
Bus Group			DataL
Rx Signal			DQ6
Iteration			3
Bus Group			DataL
Rx Signal			DQ7

4.1.4 Delay Report ^

4.1.4.1 Worst Case Summary ^

Measurement	\|Max\| InterconnectSkew (ps)	\|Max\| StrobeInterconnectSkew (ps)
Worst Value	-251.032	0
Iteration	1	1
Bus Group	DataL	DataL
Rx Signal (Waveform)	DQ4	LDQS-LDQS#
Cycle
Iteration		2
Bus Group		DataL
Rx Signal (Waveform)		LDQS-LDQS#
Cycle
Iteration		3
Bus Group		DataL
Rx Signal (Waveform)		LDQS-LDQS#
Cycle