Topology Explorer Measurement Report

- PARALLELBUS_DATA_0

Generated by Cadence SSIViewer, 22.1.0.02111.333004 000
June 29, 2022

Table of Contents

1 General Information
2 Simulation Setup
- 2.1 Model Selection and Stimulus
- 2.2 Signal Connectivity
3 Measurement Setup
- 3.1 AC and DC Logic Input Levels
4 Results
- 4.1 Eye Quality Report
  - 4.1.1 Worst Case Summary
- 4.2 Delay Report
  - 4.2.1 Worst Case Summary
5 Appendix
- 5.1 Measurement Definitions
- 5.2 Description of Abbreviations

1 General Information ^

Topology File: C:\Users\avira\Desktop\Topology Explorer Tutorial\Demo Files Part-5\PARALLELBUS_DATA_0\PARALLELBUS_DATA_0.topx
Block 'DIMM_CON' Model File: C:\Users\avira\Desktop\Topology Explorer Tutorial\Demo Files Part-4\parbus_connpin.ckt
Block 'DIMM_CON1' Model File: C:\Users\avira\Desktop\Topology Explorer Tutorial\Demo Files Part-4\parbus_connpin.ckt
Circuit Simulator: SPDSIM
Topology:

2 Simulation Setup ^

2.1 Model Selection and Stimulus ^

CNTRL_DATA

IBIS File: stratix2.ibs; IBIS Component: StratixII; OnDie Parasitics: None; Package Parasitics: None.
Signal	Pin	Data Rate (Gbps)	# of Bits	Stimulus Pattern	Stimulus Offset (ns)	Transmit IO Model	Status
SIGNAL<D6>	D6	0.532	532	10001101011100011001...	0	2s_sstl18c2_cio_d8	Signal

CNTRL_STROBE

IBIS File: stratix2.ibs; IBIS Component: StratixII; OnDie Parasitics: None; Package Parasitics: None.
Signal	Pin	Data Rate (Gbps)	# of Bits	Stimulus Pattern	Stimulus Offset (ns)	Transmit IO Model	Status
SIGNAL<D6>	D6	0.532	532	10101010..	0.94	2s_sstl18c2_cio_d8	Signal

DIMM_DATA

IBIS File: memory_dram.ibs; IBIS Component: MT47H128M4CB; OnDie Parasitics: None; Package Parasitics: None.
Signal	Pin	Receive IO Model	Status
DQ1	C2	DQ_FULL	Signal

DIMM_STROBE

IBIS File: memory_dram.ibs; IBIS Component: MT47H128M4CB; OnDie Parasitics: None; Package Parasitics: None.
Signal	Pin	Receive IO Model	Status
DQ1	C2	DQ_FULL	Signal

2.2 Signal Connectivity ^

Tx Signal	Tx Pin	Rx Signal	Rx Pin	Average Magnitude
CNTRL_DATA::SIGNAL<D6>	CNTRL_DATA::D6	DIMM_DATA::DQ1	DIMM_DATA::C2	0.500885
CNTRL_STROBE::SIGNAL<D6>	CNTRL_STROBE::D6	DIMM_STROBE::DQ1	DIMM_STROBE::C2	0.500885

3 Measurement Setup ^

3.1 AC and DC Logic Input Levels ^

Single-Ended Signals (V)

Iteration #	Signal	Corner	VIH(ac) min	VIL(ac) max	VIH(dc) min	VIL(dc) max	VREF(dc)	VDD
1	DIMM_DATA::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
1	DIMM_STROBE::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
2	DIMM_DATA::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
2	DIMM_STROBE::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
3	DIMM_DATA::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
3	DIMM_STROBE::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
4	DIMM_DATA::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
4	DIMM_STROBE::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
5	DIMM_DATA::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
5	DIMM_STROBE::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
6	DIMM_DATA::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
6	DIMM_STROBE::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
7	DIMM_DATA::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
7	DIMM_STROBE::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
8	DIMM_DATA::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
8	DIMM_STROBE::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
9	DIMM_DATA::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8
9	DIMM_STROBE::DQ1	Typ	1.15	0.65	1.025	0.775	0.9	1.8

4 Results ^

4.1 Eye Quality Report ^

4.1.1 Worst Case Summary ^

Measurement	Min ApertureWidth (ps)
Worst Value	1666.2
Simulation Result	3
Receiver	DIMM_DATA
Rx Signal (Waveform / Eye Diagram)	DQ1
Cycle
Simulation Result	6
Receiver	DIMM_DATA
Rx Signal (Waveform / Eye Diagram)	DQ1
Cycle
Simulation Result	9
Receiver	DIMM_DATA
Rx Signal (Waveform / Eye Diagram)	DQ1
Cycle

4.2 Delay Report ^

4.2.1 Worst Case Summary ^

Measurement	Min FirstSwitch (ps)	Max FinalSettle (ps)
Worst Value	698.686	1265.83
Simulation Result	1	7
Receiver	DIMM_STROBE	DIMM_STROBE
Rx Signal (Waveform)	DQ1	DQ1
Cycle	101.5	258
Simulation Result	2	8
Receiver	DIMM_STROBE	DIMM_STROBE
Rx Signal (Waveform)	DQ1	DQ1
Cycle	101.5	258
Simulation Result	3	9
Receiver	DIMM_STROBE	DIMM_STROBE
Rx Signal (Waveform)	DQ1	DQ1
Cycle	101.5	258

5 Appendix ^

5.1 Measurement Definitions ^

5.2 Description of Abbreviations ^