High-Speed Design and Analysis Environment
Allegro PCB SI provides a high-speed analysis environment that is seamlessly integrated with the Allegro PCB Designer.

It allows constraints and models to be embedded in the board design file to eliminate the risk of design translation issues. The integrated design and analysis system is aware of multi-net electrical constructs from logical design authoring to physical implementation. For example, differential pairs and extended nets (nets with a series termination) are recognized, extracted, and simulated as one electrical net from either schematic or layout. Also, I/O buffers can be modeled using many popular techniques including industry standard IBIS models and encrypted SPICE models.

SigXplorer Module Integration
SigXplorer module integrates with logical or physical design tools and provides a graphical view of I/O buffers, transmission lines, and vias...

such that complex topologies can be modified in a what-if fashion—without having to change the actual design. SigXplorer also allows engineers to sweep various parameters within the topology to identify a topology solution space, which can then be captured in the constraint management system and guide PCB designers to first-pass electrical compliance.

Constraint Management System
Cadence PCB SI technology works seamlessly with the constraint management system. Constraints derived through simulation...

can be put into an electrical constraint set (EC set) from within the topology canvas, SigXplorer. These EC sets can then be applied to other nets in the design through the constraint management system found in Allegro PCB SI. Designers can use the constraints developed through simulation and exploration and enable a front- to back-end constraint-driven design process.

Static IR Drop (DC) Analysis Technology
Allegro PCB SI includes static IR drop (DC) analysis technology that verifies that the power distribution system can provide sufficient current to drive signals.

The analysis considers effects due to trace neckdown; Swiss-cheese planes created by components with dense pin grid arrays; and reduction of available copper caused by trace routing on power and ground planes. Results can be viewed in a graphical voltage drop display or in a report that shows voltage drop at any pin that is marked as a current sink.

Advanced Simulation Capabilities
Allegro PCB SI includes a host of advanced simulation capabilities including bus analysis, EMI analysis and more.

Source Synchronous Bus Analysis Methodology
Allegro PCB SI provides a quick and easy methodology to perform post-layout analysis of all the signals associated with a source synchronous bus. It shortens the time to simulate various configurations (read/write, active, idle) associated with the functioning of source synchronous buses with or without on-die termination (ODT). The Allegro PCB SI solution allows signals to be associated and to save such associations with the design database. Users have a choice of performing reflection analysis or a more comprehensive analysis with crosstalk included. Allegro PCB SI enables engineers to derate setup and hold margins through user-defined derating tables for different signals in the source synchronous bus.

Design link (package-board or multi-board)
Interconnects from multiple PCB and IC package designs can be combined using Allegro PCB SI design link technology to analyze die to die through packages, boards, and connectors.

EMI analysis and rule-checking
Single or coupled-net EMI simulation along with a comprehensive rule-checking engine, EMControl, enables engineers to design for EM compliance. The tool included Rules development, rules checking, and differential simulation.

Model integrity
Users can create, manipulate, and validate models quickly in an easy-to-use editing environment. Support is available for IBIS, Spectre®, Mentor/Quad XTK, and Synopsys HSPICE (requires HSPICE simulator and license, which is not included with Allegro PCB SI).

Allegro PCB PDN Analysis Option
AC power integrity is accomplished with Allegro PCB PDN Analysis, an option to Allegro PCB SI. Its unique, integrated design and analysis environment...

takes the guesswork out of quantifying and controlling noise in power delivery systems. Engineers can focus on the design instead of struggling with data translation issues between the CAD system and the analysis engines. Allegro PCB PDN Analysis integrates proven technology into the Cadence design and analysis environment to address the power delivery issues encountered in high-speed design.

Allegro Multi-Gigabit Option
The Allegro Multi-Gigabit Option add a variety of useful simulation and analysis features for designers working on complex designs. 

• S-Parameter DC extrapolation
• S-Parameter generation from stack-up 
• S-Parameter plotting in SigWave 
• Time domain simulation of S-Parameters 
• Library management of S-Parameters in model integrity
• Coupled via model generator for pre-layout explorations
• High-capacity channel simulation 
• Optimum pre-emphasis bit configurations (“tap settings”) 
• BER prediction 
• Bathtub curves 
• Channel compliance—statistical analysis 
• Post-layout MGH extraction 
• Signal quality screening of routed nets