Events with EMA
The OrCAD X Platform takes the current industry-leading OrCAD Capture solution and expands it to create a PCB design tool that is faster, more automated, and more connected than ever. Cadence recently announced a strategic partnership with Sourceability, a global distributor of electronic components and supply chain service provider. Under this agreement, Sourceability’s market intelligence tool, Datalynq™, will be integrated into the Cadence® OrCAD® X Platform as Live BOM, giving you visibility into market intelligence scores for electronic components to assess and reduce design risk, as well as mitigating other supply chain risks, which will help you make better commercial decisions.
If you’re a member or leader of a PCB design team or part of procurement, join us for this webinar.
In this webinar, you’ll learn the following aspects of high-speed PCB via design.
When the via impedance doesn’t match the line impedance, it results in signal reflection and parasitic effects. To prevent this, you should position the ground vias near the signal vias to create an inductance loop for the return current. You can also implement coaxial via geometry to prevent impedance discontinuities.
While placing vias on high-speed PCB traces, always keep the stub length as low as possible to manage signal attenuation. You need to ensure the signal’s maximum frequency is significantly lower than the stub fundamental resonant frequency. In addition to this, microvias offer more reliable signal transmission compared to through-hole vias.
In RF applications, via stitching ensures a continuous and low-impedance return path. Furthermore, to block EMI from reaching and coupling with the critical signals, employ via shielding to surround the sensitive signal traces with a barrier of ground vias or metal shielding.
To route DDRs in high-frequency circuits, a fly-by topology is ideal. It sequentially connects each memory module with the main controller, minimizing signal path length with fewer branches than T-topology.
When breaking out 0.4 and 0.5 mm BGAs, incorporate via-in-pad. It involves placing multiple vias directly under the solder pad where the BGA ball is attached. Employ non-solder mask-defined pads if your design allows enough room between adjacent BGA pads.
To eliminate the risk of annular ring breakout and drill wander in high-speed PCB vias, precise annular ring calculation is crucial. Additionally, prefer staggered microvias over stacked if your board fabrication needs more than 3 lamination cycles. This will reduce the risks of barrel and corner cracking.
In this webinar, the EMA and Sierra experts will practically demonstrate the best practices for designing high-speed PCB vias.
Network with peers, colleagues and experts at PCB East 2024. Connect with fabricators, assemblers and engineers from around the world. It’s the place to be in the Northeast.
We’re ready to welcome the global 3DEXPERIENCE® Works ecosystem back to Dallas, TX for 3DEXPERIENCE World 2024. Whether you are a long time SOLIDWORKS user, just starting your product design journey, or using the extended 3DEXPERIENCE Works concept to manufacturing solutions, like DELMIAWorks, 3DEXPERIENCE World will provide connection to the technologies, trends, and leaders to help you create new products, new lines of business or new experiences.