CADENCE SYSTEM DESIGN & ANALYSIS

Sigrity Unified Analysis Workbench

Complete electrical analysis platform built to help you solve all your SI, PI,  and EMC design challenges across the board 

Solve The Next Generation Of Design Challenges with Sigrity

Designs are not getting simpler and delivery schedules aren't getting longer. If you hope to stay ahead of the competition, you must determine optimal design configurations, validate performance, and signoff on your critical interconnects well before you get to prototype . Sigrity provides the only complete analysis solution designed to solve todays multi-physics, multi-domain design challenges.

Guided, Workflow-Driven Analysis

EASY

Guided, Workflow-Driven Analysis

Figuring out how to set up the simulation shouldn’t take twice as long as the analysis. Sigrity provides easy to follow workflows and wizards designed to guide you through the simulation setup and analysis process quickly and efficiently. Coupled with a comprehensive model library and management environment you have a quick repeatable path to analysis that can be leveraged throughout your organization.


Learn More About Workflows >

Pre & Post Layout Insights

FAST

Get to Actionable Insights Quickly - Pre & Post Layout

Along with reduced setup time, Sigrity boasts the fastest analysis engines on the market. Up tp 10x faster run-times than other leading engines, Sigrity is optimized to meet the challenges of todays complex analysis requirements. Full multi-threading threading support allows you to accelerate this speed-up even farther by leveraging your multi-core compute resources to go from run to results in no-time.


Learn More About Compliance and Reporting >

Hardware-Correlated Results

ACCURATE

Hardware-Correlated Results

Analyze and verify with confidence knowing your results will have tight correlation to real-world hardware. Your analysis is only as good as the confidence in your results. Cadence rigorously tests Sigrity against their own hardware ensuring the correlation you need to sign-off with confidence.

Analyze in Your Environment Seamlessly

MULTI-CAD

Analyze in Your Environment Seamlessly

Regardless of your CAD environment it is easy to bring your data into Sigrity for quick and accurate analysis. Simply drag and drop your design files on the unified canvas and start running workflows. Leverage the automated reporting engine to quickly generate and share insights from your analysis with colleagues drastically cutting down on reporting time.


UNIFIED LAYOUT WORKBENCH

ONE ENVIRONMENT. ENDLESS POSSIBILITIES.

Signal Integrity

Impedance | Coupling | Crosstalk
Noise | TDR/TDT

Power Integrity

IR Drop | Resonance | Impedance | Loop Inductance | Thermal

Thermal Analysis

Transient & Static Electrical
Thermal Co-Sim | FEA | CFD

EM Analysis

Model Extraction | Full 3D EM
S-Parameters

ESD

Virtual ESD Gun | TVS Analysis

EMI/EMC

Near Field | Far Field | SAR 
Radiated Emissions | Cap Optimization

Channel Analysis

DDRx | USB | PCI-e | MIPI | HDMI
SATA | Serial | Parallel | AMI Modeling

Topology Exploration

SI | PI | Solution Sweeps
Requirements Definition 



THERE'S A WORKFLOW FOR THAT

The unique workflow-driven design environment and comprehensive simulation engines allow you to quickly access and perform the analysis needed to meet your design needs. As your analysis requirements increase, it is easy to add additional workflows all within the same common UI.

Identifies the source of reflection and noise by detecting impedance discontinuities and ensuring adherence to defined impedance constraints.
Prevent signal degradation of critical nets due to overshoot, undershoot, and ringing by identifying reflections caused by mismatched impedance.
Identify critically coupled traces within the PCB layout canvas to ensure adequate spacing and optimal signal quality.
Easily determine interference caused by unwanted capacitive, inductive, or conductive coupling from one circuit or channel to another and improve signal quality throughout your design.
Prevent divergence between ideal simulation and measurement by analyzing and identifying return path discontinuities to ensure uninterrupted references and an optimized return path.
Provides measured indication of switching noise (and other types) on specific power/ground traces & shapes to reduce noise on other signals attached to the same plane.
Easily check the signal's propagation, reflection, and impedance discontinuity by step pulse response which can better show voltage and impedance variation with time.
Easily model, simulate, and analyze topologies to evaluate signal integrity performance for complete serial link interfaces.
Provides full time-domain analysis for parallel bus protocols and supports a variety of IBIS and AMI protocol setups, including the newer/faster protocols reliant on serial channel methodologies, to determine performance compliance.
Create realistic simulations with the easy and convenient extraction of S, Z, and Y parameters of multiple port networks that model package and board structures.
Perform pre-layout and post-layout electrical analysis of the entire package and board through user-defined “W-element” for stack-up characterizations and full parasitic model extraction of layout geometries for time domain analysis of interface designs.
Ensure proper power levels are delivered to devices through single-Board, multi-board, or package IR Drop analysis of the static power delivery system on PCB from multiple VRMs to CPU and DIMMs.
Determine power loss through analysis of the DC resistance from a source to a load.
Analyze system-level power loss for your entire PDN through the generation of a resistance network matrix based on the terminals specified by the user.
Quickly identify high resonance, which may cause EMI issues, by analyzing adherence to target impedance.
Quickly evaluate the effectiveness of capacitor locations by computing the loop inductance of each capacitor observed from the given devices on the same power rail to ensure adequate power can be delivered when required.
Identify weak pins by measuring individual inductance and analyzing the capacitors placement effect on pins.
Determine the best location for capacitor placement to reduce resonance within the PDN which can cause EMI radiation.
Improve pin effectiveness with the easy detection of high resistance between the source (VRM) and load (pin) to reduce the likelihood of overheating.
Prevent electrical spikes by identifying resonant modes between predefined frequency ranges.
Determine the effects of external power delivery, conducted emissions, and coupling paths to reduce noise on the PDN.
Easily solve both electrical and thermal equations simultaneously through single-board/package or multi-board/package 3D finite element methods.
Ensure adherence to JEDEC standards through the easy extraction of thermal parameters such as lead frame packages, BGAs, wire-bonds, package-on-package (POP) and system-in-package(SIP), flip-chip packages, and more.
Accurately analyze the PDN with the easy extraction of S, Z, and Y parameters of multiple port networks that realistically model package and board structures.
Analyze near-field E/H densities and radiation effects from traces and edges to easily identify problematic EMI radiating devices and the extent of noise to determine necessary shielding and faraday cage placement.
Evaluate the current/voltage induced on the PCB or package through an external plane wave source to accurately determine the impact of external radiation and overall system susceptibility
Provide accurate EM solutions for complicated 3D structures with 3D finite element analysis tools and adaptive mesh refinement tailored to IC package and PCB designs.
Realistically replicate the testbench environment defined in IEC-61000-4-2 and easily inject ESD pulses at specified points to emulate and analyze the effects of a physical ESD gun on the design.
Create realistic simulations with the easy and convenient extraction of S, Z, and Y parameters of multiple port networks that model vias, connectors, and components.



AUTOMATED COMPLIANCE & REPORTING

Easily Communicate Your Results & Insights In Real-Time

For complex interfaces like DDR or PCI, manually reporting on all the data points needed to guarantee compliance is error-prone and can take hours to create. With Sigrity, the reports and documents needed to communicate with project stakeholders are just another output of your simulation and analysis activities. Documents are easily sharable and consumable in HTML format. Compliance reports are auto-configured based on the interface specifications, ensuring you are documenting all the key metrics needed for sign-off.

Download our PCI-e ebook >

SERIAL LINK

Automated SerDes Analysis

Ensuring your key serial interfaces operate as intended is not easy. Sigrity allows you to move to production with confidence  by providing a complete sign-off level design, analysis, and compliance environment for your critical serial links.


Key Capabilities

  • Wizard-driven workflows makes setup and analysis easy
  • 10x performance to competitive solvers with no loss of accuracy
  • Built-in pass/fail compliance checking for major serial interfaces (PCIe, HDMI, SFP+, XAUI, SAS, SATA, USB, etc)
  • Best-in class vendor independent IBIS-AMI model support
  • Full channel analysis to concurrently identify crosstalk, CDR, SSO, and confirm BER over millions of bits

PARALLEL BUS

Power-Aware DDRx

Achieve first-pass success for your DDR interfaces with Sigrity. Quickly model and analyze these complex interfaces with hardware-level accuracy at any stage of your design with the easy-to-use, Sigrity-guided workflows.


Key Capabilities

  • Wizard-driven workflows makes setup and analysis easy 
  • 10x performance to competitive solvers with no loss of accuracy
  • Power-Aware analysis included to ensure hardware level accuracy 
  • Support for all generations of DDR including the latest DDR5
  • Account for ISI, Crosstalk, Reflections, and SSN
  • IBIS-AMI model support to incorporate equalization and other and other controller learning and adjustment capabilties

Download Whitepaper: Power-Aware DDR Analysis 


Take the Sigrity Challenge

The Results Speak for Themselves. Want to see how Sigrity can help you? Take the Sigrity Challenge to get a complimentary design review and let us show you the results on one of your designs.

Cadence Optimized

See how the best-in-class Sigrity and Allegro engines combine to enable true electrically-aware design from start to finish with Sigrity Aurora.

Multi-Physics Analysis

Learn more about the electromagnetic, electronics, thermal, and electromechanical simulation solutions Cadence has to offer.

Schedule A Demo

How Can We Help?

Resources