Sigrity X
Product Documentation in PDF Format Removed from the Install Media
- All
To reduce overall media size and improve installation time, product documentation in PDF format is no longer included in the install media. The PDFs can still be accessed from the Cadence ASK site or the CDA online mode.
Cloud-Based Doc Assistant
- All
The cloud-based help system, Doc Assistant, has been upgraded to version 25.10, which contains several new features and enhancements over the previous version.
User Interface Improvements in Layout Workbench Tools
- Layout Workbench
All Sigrity Layout Workbench tools feature an intuitive user interface consisting of reorganized menus, streamlined toolbars and options, and vibrant icons to boost efficiency and productivity. In previously releases, UI improvements were available via the User Improved User Interface checkbox. Starting with 25.1, the checkbox has been removed, and the improved UI is available by default.
Quick Access to Shipped Examples
- Layout Workbench
The File menu provides a new option, Open Example, for quick access to the examples shipped with the installation. This option lets you access all samples and examples with a single click with no need to manually search in the install directory.
Edit Cutting Boundary Dialog Box Enhanced and Renamed
- Layout Workbench
The Edit Cutting Boundary dialog box has been enhanced and renamed to the Edit Cutting Polygon dialog box with several options added to provide advanced polygon cutting capabilities. The dialog box can be accessed from the Summary Cutting Polygon icon on the Processing toolbar.
Incremental Structure Update in PowerTree
- PowerTree
PowerTree supports incremental updates to the topology tree, allowing changes from the schematic to be reflected without rebuilding the entire tree. When a new netlist is generated with minor updates, only the affected portions of the tree are updated. This approach saves time and maintains the existing structure and settings.
Preview Reused Stackup Results in Reuse Stackup Dialog Box
- Layout Workbench
The Reuse Stackup dialog box now shows a preview of the reused stackup results in a dedicated pane called the Preview Layers panel when reusing stackup settings form another SPD file. This capability ensures that the reused stackup results are consistent with your simulation goals.
Translator Settings Reorganized
- Layout Workbench
The translation settings available under the Settings tab have been functionally organized under dedicated categories to provide an intuitive experience to Layout Workbench users.
Translation Setting Added to Dielectric Mask Layer Options
- All
A new setting, Translate Non-Metal Stiffener Shapes into Dielectric Blocks, has been added to convert non-metal stiffener shapes into dielectric blocks during translation. This option is available in the Rigid-Flex tab under Dielectric Mask Layer Options.
Coplanar Stripline Template Added to Trace
- Layout Workbench
A new transmission line template, Coplanar Stripline, has been added to the Trace Editor dialog box.
Python Command Updates
- Layout Workbench
New and updated Python commands have been added across multiple Layout Workbench tools. The pydoc module can be used to generate the documentation for these commands automatically. An HTML file, sigrity.html, is generated in your home directory. You can open the file in a browser window to view the Python documentation.
Thread Usage Limitation Across Flows – Licensing and Performance Considerations
- All
To ensure consistent licensing behavior and optimal performance, the number of CPU cores allocated per engine instances is now limited to 8. This serves as a safeguard, as license are typically checked out in increments of 8, and assigning more than 8 CPUs to a signal instance may degrade performance.
New Package Type
- Package eXtractor
A new package type, Direct Die to Die, is added to the Package Setup > Package Type panel. This package type lets you extract the model between die to die directly without BGA. When using this type, ensure that one of the dies is assigned as the Main Die when selecting components in the Wizard dialog box.
Circuit Generation Wizard Improved
- Optimize PI
The Circuit Generation Wizard now allows selection of all power nets at once during the Impedance Observation and Decoupling Capacitors setup. The Power Net dropdown includes an option for PowerNets, which allows you to select and display all power nets simultaneously.
Undo Operation Enabled for Several Setups
- Optimize PI
The Undo operation is now supported for actions such as deleting and disabling impedance operations, editing frequency range, and deleting VRMs or decoupling capacitors.
TCL Command Updates
- Optimize PI
The flowing TCL commands have been added and enhanced with the new version.
sigrity::add reusePort -type {vrm|decap|obs} -name {ob*| ob1, ob2, ob3} -path {file path}
: Reuses the ports from the SPD file and defines them as VRMs, impedance observations, and more.sigrity::update simulation -startFreq {value} -endFreq {value}
: Specifies the frequency and time range for a simulation.sigrity::update simuType {OPTI|WhatIf|StatisticalAnalysis} -optiType {Chip|EMI}
: Configures the analysis type as Device Optimization, What-If Analysis, and statistical analysis for a simulation run.sigrity::update deviceOPTI -name {value} -opiObjective {type}
: Specifies the optimization objective for a Device Optimization simulation run. The following objectives can be specified:- Best Performance vs. Cost
- Best Performance vs. Area
- Best Performance vs. Number of Capacitors
- Best Performance Schemas Overall
sigrity::update impedanceObservation {object name} -enable {true|false} {!}
: Selects an impedance observation function.sigrity::update mutualImpedanceSelection -enable {true | false} -portName1 {name} -portName2 {name} {!}
: Selects a mutual impedance observation function.
SI Metrics Automation Workflow
- PowerSI
The SI Metrics Automation workflow has been added to automate the PowerSI S-Parameter Assessment workflow. The new workflow provides automated layout-level signal integrity performance evaluation. This workflow can be used to quickly compare up to three board designs with comprehensive signal integrity metrics and waveform visualizations. This workflow is available as a separate executable, SIMetrics_Automation.exe, in the tools/bin directory of your local installation.
Multiple Structure Simulation Workflow Enhanced
- PowerSI
The Multiple Structure Simulation workflow in PowerSI includes several enhancements in the GUI to provide users with more ease and flexibility. The workflow pane in both Diagram View and 2D View is updated to display relevant configuration options. Additionally, you can directly access the details of each block present in a topology by right-clicking and selecting the Load Block button.
Updated Reporting Options
- PowerSI
In the S-Parameter Assessment workflow, the Report dialog box now includes new options to include in the simulation report, including frequency domain, time domain, and other performance metrics.
Wirebond Support
- PowerSI
In the ERC – Trace Imp/Cpl/Ref Check workflow, an option to Include Wirebond while Calculating Impedance/Coupling has been added to the Set up ERC Sim Options dialog box. Check this option to view the impedance and coupling in the wirebonds present in the design.
New Tutorials Added
- PowerSI
The following new tutorials have been added to the Sigrity/Systems Analysis documentation set:
- SI Metrics Automation Workflow Tutorial: This tutorial explains the tasks and steps required to simulate and compare board designs with the new SI Metrics Automation workflow.
- PowerSI EMC/EMI Simulation (Radiation) Tutorial: This tutorial walks you through the tasks and steps required to simulate and analyze the radiation effects from traces and edges in designs.
Label-Based Node Generation
- All
A new command, GDS_LABELPADLAYER
, has been introduced to generate nodes based on labels, offering greater flexibility over the existing polygon-based method.
Option to Import Dual ICT Files
- All
You can now import and merge two ICT technology files with configuration within the technology file to make multi-source integration easier.
Metal Touch Support in IC Mode
- Layout Workbench
Metal-to-metal touch in IC Mode has been added to Layout Workbench Tools. When disabled, a medium layer is automatically inserted between adjacent metals.
Log File Renamed
- All
The log file previously saved as error.logfile is now saved as translation.log for the GDS to SPD translator to provide an accurate representation of the file content.
Windows Support for Encrypted IRCX Files
- All
Support for encrypted IRCX stackup files is now extended to the Windows operating system.
GDS to SPD Tutorial Integrated into Translators User Guide
- All
The GDS to SPD Tutorial has been removed as a standalone document and its content has been added to the Translators User Guide.
Advanced Design Extraction Workflow
- XtractIM
A new workflow, Enhanced Design Extraction, is now available to use in XtractIM. This workflow enables you to solve the RLC between dies and capacitors without BGA, use an existing uBump without adding an extra bump for dies, and create a compressed and compact SPICE model.
Pin Group Editor
- XtractIM
A new button, Advanced Group Editor, has been added to the MCP Auto Connection window. This button opens the Advanced Group Editor form where you can edit pin groups after importing a PLOC file.
Parameters to Support PDN Domain
- T2B
The Component parameters now support the PDN domain, marking the beginning of a specification that describes the connection between two pad rail terminals through an on-die decoupling capacitance PDN model.
Support for Multi-Layer Structures Between TSV and TSV Bump
- XcitePI
XcitePI has been enhanced to handle interposer cases with multiple metal layers between TSVs and TSV bumps. This update also introduces support for adding BRDL_VIA layer via shapes to represent advanced packaging designs.
Options for Defining TSV Bump Parameters
- XcitePI
Support has been added for specifying key physical and material properties of TSV bumps to enhance customization options.
XcitePI TCL Command Updates
- XcitePI
The following TCL commands have been added to XcitePI.
xpi_ckt_def_remove{<ckt_definition_name>}
: Deletes the circuit definition of the specified name.xpi_set_net -net {<net_name>} -enable [0 | 1] -visible [0 | 1] -color <color_value>
: Enables the net, maxes it visible, and sets its color for better visibility.xpi_set_window{<llx>,<lly>,<urx>,<ury>} [<orig_gds>][-residual_remain [0 | 1]]
: A new option (residual_remain) has been added to remove the cutting residual.xpi_set_tsv[-level <N>] er_ox <value> thick_ox <value> [-er_ox1 <value>][-thick_ox1 <value>] [-er_ox2 <value>][-thick_ox2 <value>] [-via_cond <value>][-sub_cond <value>][-ckt <Ckt_Def_name>][-bump_node <uBump_name>][-m1_node <M1_node_name>][-gnd_node <GND_node_name>][-vth <value>]
: New options, thick_ox2 and er_ox2, have been added to define the third oxide layer.
Performance Improvement in Broadband SPICE
- Broadband SPICE
Broadband SPICE now leverages MPI-based passivity enforcement in multicore mode for improved performance. This feature, which is enabled by default, can be deactivated by setting the BBS_MPIPE environment variable to 1.
DC Resistance Workflow
- Aurora
A new workflow, DC Resistance, is available in the Analysis Workflows of Sigrity Aurora. This workflow computes the DC resistance for specific power and ground nets present in a design. Use this workflow to compute partial resistance or loop resistance for lumped-to-lumped or multiple-to-multiple measurement models. The analysis results of this workflow are displayed in resistance tables that show the measured partial and loop resistances along with a pass or fail status.
3DX Viewer
- Aurora
A new 3D canvas, Allegro 3DX Canvas, is available in the Interconnect Model Extraction and Topology Extraction workflows for displaying and analyzing 3D net geometries. The new 3DX canvas displays the 3D preview prominently, minimizing surrounding options and controls to create a clutter-free viewing experience.
Customizable XML-Based Workflows
- Aurora
Sigrity Aurora supports customizable, XML-based workflows to add custom content to the analysis workflows. The custom XML file, ida_custom.xml, can be edited to add content, such as links or custom groups with links, to the existing workflows.
Multi-Die Support in Thermal Workflow
- Aurora
The Thermal Workflow now includes multi-die support.
Layout Link Setup in Topology Extraction Workflow
- Aurora
The Topology Extraction Workflow now supports topology-driven LayoutLink setup to provide the multi-layout SI simulations capability from the layout itself.
User Interface Improvements in Analysis Model Manager
- Aurora
Analysis Model Manager includes an option to activate an improved user interface, aimed at supporting an enterprise-level signal integrity library implementation.
Sigrity Aurora User Guide Added
- Aurora
A new document, Sigrity Aurora User Guide, has been added in this release. This document describes how to use Sigrity™ Aurora PCB Analysis for checking and analyzing potential signal integrity and power integrity problems. Additionally, the document walks through the user interface elements and various dialogs, windows, and options to configure and run the integrated analysis workflows.
Subsystem Block
- Topology Explorer
A hierarchical structure can be created with a new subsystem block for topology simplification and design reuse. This new block is available in Topology Explorer, Serial Link Analysis (SLA), Parallel Bus Analysis (PBA), SystemPI (DC IR Drop Analysis, PDN Impedance Analysis, and Power Ripple Analysis).
2D Curves Viewer Option
- Topology Explorer
Reopen the 2D Curves tab with the new 2D Curves Viewer option in the Tools menu.
Modeling of Traces over Cross-Hatch Planes
- SystemSI
The Trace Editor includes the Edit Cross-Hatch Plane Library button to model traces over cross-hatch planes. This feature helps evaluate transmission line propagation constants and impedance during the pre-layout stage of rigid-flex design, ensuring optimal performance.
Layout and Clarity3D Block Constraint Backannotation
- SystemSI
For Layout and Clarity3D blocks, optimized parameters from Sweep Manager or Optimality can be written to a constraint file and backannotated to the Allegro X Constraint Manager.
Tx Jitter Extrapolation for Time Domain and Statistical Simulations
- SystemSI
All Tx jitter present in an AMI model or the Analysis Options panel can be included in the post-processing of the jitter distribution collected over the duration of the simulation.
Steady-State Auto Detection for Characterization Waveforms
- SystemSI
The Characterization Options section of the Options form allows the minimum and maximum time for automatic detection of the steady state for characterization waveforms can be defined. The circuit simulation stops after the steady state has been reached.
Statistical Simulation Stimulus Offset
- SystemSI
With the Statistical Simulation option selected in the Channel Simulation tab of the Analysis Options panel, the IO Models and Stimulus tab allows for a stimulus offset for statistical simulations.
AMI Builder Supports Use_Rx_Clock_Input
- SystemSI
In the Parallel Bus Analysis workflow, the AMI Builder Wizard allows the creation of AMI models that support Use_Rx_Clock_Input from clock or strobe signals.
Electromagnetic Interference Workflow
- SystemSI
The Electromagnetic Interference Simulation workflow can be accessed through the properties of the FDTD-D (Finite Difference Time Domain) block.
New Compliance Kits Supported
- SystemSI
The following new compliance kits are available in release 25.1.
- CEI-56G and 112G Medium Reach (MR) Compliance Kits: These compliance kits are used to verify that electrical interferences in networking equipment meet the specifications defined by the Component Electrical IO (CEI) processes for high-speed data transmission.
- MPDI-D Compliance Kit: This kit is used to support differential data signals and to verify that a device’s implementation in the MIPI D-PHY interface adheres to the MIPI Alliance specifications to ensure interoperability and reliable communication between components.
- UCIe Compliance Kit: To support the Universal Chipset Integration Express (UCIe™) Specification v2.0, Topology Workbench offers templates designed for data rates of 16 and 32 Gbps. These templates provide generic IBIS-IMI models and reference channels for both data rates, facilitating improved modeling and simulation of UCIe interfaces.
New DDR5, LPDDR5, and UCIe-Compliant Templates in PBA Window
- SystemSI
New templates have been added to the Parallel Bus Analysis workflow for DDR5 and LPDDR5/5X.
Stressed Eye Measurement in PBA Measurement Report
- SystemSI
The StressedDiamond option is now available in the Mask list in the Measurement Customization window. This option can be used to review stressed eye measurements from the generated measurement report in the Parallel Bus Analysis workflow.
PDN Impedance and Power Ripple Analysis Workflow Supports Optimality
- SystemPI
- Optimality Explorer
Starting with this release, Optimality Intelligence System Explorer is now supported in the PDN Impedance and Power Ripple Analysis workflow.
Target Impedance Block
- SystemPI
A new Target Impedance block has been added to set the resistance and inductance ranges. Only one Target Impedance block can be added to a canvas, and the other blocks on the canvas must be included in its netlist.
What-If Decap Models Enhanced
- SystemPI
Multiple instances of decap models can be assigned to a single what-if block for sweeping. In the Sweep Manager, a single instance of multiple decap models can be swept.
SystemPI Report Generation
- SystemPI
The Generate Report dialog box now has checkboxes to select specific simulation results to include in the report. Additionally, options are available to include frequency spectrum plots with plotting options to show the frequency axis in the log scale and minor gridlines.
Current Check Options
- PowerDC
The Auto Check Pin Current dialog box includes two new options to balance positive/negative pin current and use absolute values to balance the unequal positive and negative currents imported from the Current Mapping file.
Efficient Search Integrated in Component Search Wizards
- PowerDC
The search functionality in the Set up VRMs, Set up Sinks, and Set up Discretes wizards has been improved to efficiently search for components by name. The Up and Down radio buttons have been removed to provide a simple and effective component search.
TCL Command Enhancements for Creating Partial and Loop Resistances
- PowerDC
The add pdcResist TCL command used to create resistances for all power and ground nets connected with two nodes or components has been improved to create resistance for a specific power or ground net. Additionally, enhancements have been made to support lumped to lumped, lumped to multiple, multiple to lumped, and multiple to multiple models.
TCL Command Updates
- PowerDC
The following TCL commands have been added to PowerDC:
sigrity::query PDCdistribution -layer {name} -result {type} -net {net1, net2, net3 ...}
: Generates the hotspot and coldspot point locations within a specific distribution result, such as current, current density, voltage, power density, power loss, and IR drop.sigrity::save LayoutView -FileName {filename.png | .bmp}
: Exports and saves the layout displayed in the 2D view as an image file in the PNG or BMP format.sigrity::export pdcSinkPinRelativeVoltage -filename {filename.csv}
: Calculates and exports the voltage values between every set of positive VDD and GND pins in proximity to each other in a layout design.sigrity::set UnequalPosNegPinBalance {1| TRUE}
: Reverses the polarity of the current value for all positive pins when the current mapping file is imported.sigrity::set pdcViaMaxDisplayLength {threshold_length}
: Controls the trench via distribution displayed in the 2D view according to a user-specified threshold value.sigrity::set pdcNodeEquipotential | pdcpdcNodeEp -Node {node_name} - Equipotential | -EP {0|1} {!}
: Sets a node as an equipotential node.