Allegro/OrCAD/PSpice Version History

The Cut and Undo Cut options in the Artwork Control Form window can now be used to remove and restore selected item film layers in a single action. When multiple film layers are selected under the Film Control tab, right-clicking any one of them and choosing the Cut option removes all selected layers at once, and selecting the Undo Cut option restores all of them in a single operation.

Product features have been updated with significant performance improvements including Find by Query, In-Design Analysis, Placement and Interactive Placement, Degassing, Shape Voiding, SKILL, and more.

Saved queries can now be reused as filters with additional refinements. Loading a saved query from the By Saved Query option in the Find filter, the graphical filter settings for previously active filters are reset. If a command is already active, the query refreshes the filter setting for unsupported elements. Also applies to SKILL-based commands.

Allegro X PCB Editor now supports the photo width text parameter and OpenType fonts in the GDSII stream format. This enhancement enables accurate export of etch-layer text when data is exported from a physical design to the GDSII stream format.

TI model libraries can be accessed directly from Component Explorer in OrCAD X Capture. Right-click TI-PSpice under Workspace Configuration and choose Show Component Explorer. Requires a valid OrCAD X Cloud subscription.

When you compare two design versions through the Project Explorer or the Version Control dialog in Allegro X System Capture, a new Comparison dashboard provides a visual overview of differences between design versions. This dashboard is available in both Individual Mode and Collaboration Mode and offers two ways to add differences:

• Tree view: organizes changes by design hierarchy, helping you navigate blocks and locate modifications within the design structure
• Flat: displays all detected differences in a single list for quick scanning

This release introduces an enhanced simulation workflow in the System Capture environment to support Power Module design analysis. With this workflow, you can:

• Create dedicated simulation schematics directly from implementation schematics.
• Select specific regions of the design for simulation.
• Annotate designs with parasitic models using external .ckt files.
• Automatically translate required libraries during workflow setup.
• Automatically generate symbols for simulation components.
• Correctly map ports and pins between schematic components and parasitic blocks.

The metal density scan procedure is enhanced to improve density analysis between two regions on the same layer.

• Scan Procedure Option: A new Region compare option allows evaluation of density differences between selected regions. It checks whether they overlap or are on the same layer.
• Scan Option: A new Scan region inner option is available within the Region compare scan procedure to define the reference region used for comparison.

A new quick report has been added and provides conductor lengths within a selected region across all layers. This information helps quickly understand how much routing lies inside or outside a region. It also provides automatic, clear labels indicating how nested or overlapping regions are handled.

A new quick report has been added and provides both layer‑wise and total length comparisons for the member nets of a differential pair. This information helps in quickly identifying length differences(deltas) between member nets and supports more accurate differential pair tuning.

CIP Software has been migrated from Microsoft .NET Framework 4.8 to Microsoft .NET 9.0.

Refreshed user experience and interface throughout CIP with a new and improved GUI.

CIP users can now select their preferred theme; System, Dark, or Light, to align with their OrCAD preferences.

Text fields for Part Type and Schematic Part now allow 512 characters. User fields 71-75 now allow 1024 characters. Reference Designators now allow 31 characters, matching the default for other OrCAD products.

New example CIS .DBC files have been added for compatibility with the CIP 8.0 database.

The ability to place and preview parts from the Part Type search has been added increasing efficiency for part research and selection.

Line numbers have been added to each page of results for Quick/Keyword searches, CIS Database searches, and History searches. These are meant for reference only.

A progress animation has been added to various pages that may take a wile to load, indicating an action is in progress and preventing multiple clicks.

Paging has been added to History Search results and the Temporary Parts list (along with a total match count) for efficient review.

Field groups for Distributor and Compliance searches are now collapsible to condense views as needed.

Compliance Sync now shows “Scheduled SiliconExprt Sync” in the Last Modified By field for a scheduled sink and the current CIP user for a manual sink.

Build Rule Blocks can now be reordered providing flexibility and customization.

More info has been added to the confirmation window when saving a field across all views.

Tooltips in Field Permissions have been updated.

Warning descriptions have been added to customizable fields to help understand when an update may be required.

Timeouts have been removed to minimize errors during database upgrades. Upgrades will now proceed until completed or canceled.

The default view is now “Select a View” when using Replace Part from Design Parts Sync and the part number is not found.

The metal density scan has been enhanced with polygon-based region selection which also supports voids. To improve usability, scan region labels now specify the shape type, rectangular or polygonal, and related option names are clearer.

Simplify design reusing by replacing file-based methods and place replicate methods with a direct clipboard-based workflow. You can now copy placement, routing, vias, and shapes between designs without intermediate files, saving time and accelerating design cycles. This method includes intelligent mapping for a seamless transition. Upon pasting, a dialog box guides you through the correct integration of the copied layout into the target design.

The status command dialog box has been updated with new fields, providing enhanced visibility and control over the status of design shapes. This includes:

• Degas shapes: Reports the number of out-of-date degas shapes and provides an Update Degas option.
• Metal Fill Shapes: Reports the number of out-of-date metal fill shapes and provides an Update Metal Fill option.
• Deferred Shapes: Reports the number of deferred shapes and provides a Defer All Off option.

Cadence is committed to continuous improvement of the performance of its products, which, in turn, impacts your productivity. Performance enhancements are included for design synchronization, DFA, Find by Query, placement and interactive placement for modules, via arrays and via structures, net loop report, routing and interactive routing and more.

The following new SKILL functions have been added:

• axl3DXGetDesignOption: Returns the value of a 3DX design option for the current design database
• axl3DXSetDesignOption: Modifies the value of a 3DX design option for the current design database.
• axlShapeFreezeAll: Identifies all dynamic shapes in the design that are not frozen and sets their status to frozen.
• axlShapeIsFrozen: Checks whether a given dynamic shape is frozen, returns nil if the shape is not dynamic.
• axlShaeSetFrozen: Identifies the list of provided shapes and updates their frozen status based on the specified status flag.
• axlShapeUnfreezeAll: Locates all frozen dynamic shapes in the design and changes their status to unfrozen.

Snapping control has been enhanced and snapping configuration simplified. A new keyboard shortcut has been added to toggle snapping and snapping cursor display without leaving the layout editor, reducing workflow interruptions. A new All check box to activate snapping for all objects has been added, streamlining snapping configuration.

Enhancements to the text viewer streamline the analysis of log and report files to accelerate debugging and verification. The viewer is integrated as a dedicated tab in the user interface and is functional across workspaces. With this update you can identify critical messages with keyboard highlighting to include severity:

• Error (red)
• Warning (yellow)
• Info (green)

Additionally, the text viewer now automatically converts X,Y coordinate pairs in log and report files to clickable hyperlinks. Clicking a link centers and zooms the design canvas to that location for one-click navigation.

Cadence is committed to continuous improvement of the performance of its products, which, in turn,
impacts your productivity. These improvements are driven by your suggestions, technological
innovations, expected or current market changes, and in-house research. Many updates have been included in this release including performance improvements for design rule checks (DRCs), via arrays, daisy chain generator, shapes, placement, and interactive placement.

With this release, OrCAD X Presto introduces the ability to perform instant fanout on multiple pins. Draw a window around a group of pins to select them to perform the instant fanout.

Starting with this release, when a DRC is selected from the Search panel, the visibility of the layers containing that DRC is automatically enabled, even if those layers were previously hidden. This improves the DRC selection mechanism, enhances usability, and allows for immediate viewing and analysis of the selected DRC without requiring manual adjustments to layer visibility.

With this unified cockpit designers can seamlessly edit, plan, and modify the PCB layout with the easy-to-use X Layout platform directly in System Capture. This change enhances collaboration between the schematic and PCB layout and incorporates additional features such as preferences and constraints to help communicate design intent upfront.

The System Capture system-level design workflow is upgraded to improve complex multi-board project handling and design reusability. Key enhanced features include:

• Multi-Page Logical Board Placement: You can now place parts of the same logical board on different schematic pages and use the same logical block multiple times in other parts of the design.
• Ignore Subsystem Option: A context menu, Ignore Subsystem, has been introduced to exclude specific subsystems from system-level connectivity checks and report generation.

System Capture now supports generating navigation link reports, also called cross-references or CRef reports. Reports for Nets by Page, Base Net, Pin Cross-References, CRef parts, and Synonyms can now be created to be viewed in the schematic or exported as text files. These reports provide detailed connectivity and component cross-referencing insights to help quickly analyze design relationships and locate elements across pages and blocks.

System Capture designs now handle cells with the same names across libraries. To support this enhancement, physical part names are modified to avoid conflicts.

SnapMagic is now available in Unified Search to expand the list of available components. The SnapMagic parts database can be accessed without leaving System Capture.

You can now run electrical stress analysis on a specific device such as an IC, connector, DC-DC/LDO, or mechanical device.

A new workflow to streamline electrical stress analysis has been introduced. The EOS workflow can be accessed under View > Analysis Workflows > Electrical Stress.

Separate dashboards to analyze pre-layout and post-layout power topology analysis results are now available.

The Pulse web dashboard now supports design variants. To choose a variant, open the Schematic tab and select the Variant dropdown. This enhancement allows designers to switch between variants and easily review or download them.

System Capture and the Pulse web dashboard have enhanced design search and version control capabilities. These include:

• • • • • • • • • The MATCHES column shows BOM-Only Components and Variant Components for design search results.
                • Version control for designs and blocks is available in the Design tab of Unified Search.
                • A new filter called Reuse From has been introduced. This filter shows the source of the design block that is reused.
                • A new Reuse section has been added to the project Details tab. This section provides quick access to details of an imported block. This section shows key information for the block plus version information.
                • The Version Control window now supports version management at the block and page levels.

With the new Local Library feature, create and manage libraries directly on your computer. With this new feature, a pulse server connection is not required, all symbols are edited and stored locally with complete formatting support. Anyone can author these local libraries and no role-based restrictions apply. Additionally, custom shapes from managed libraries can be reused and importing pin lists for faster symbol creation is available.

Validation rules now offer enhanced customization for system-defined rules, with the ability to specify the object stages in which they run, such as Validate, Check-in, Pre-Release, and Release. User-defined rules can now be created for all library object types, beyond libraries, parts, symbols, and footprints.

Multi-package support is now available for library symbols. Multi-packages are symbols with the same number of pins but different pin configurations. A sectioned symbol, such as a 4-pin symbol split into four single-pin sections, is also considered a package. This new feature helps to manage different package variants of the same component.

In the Collaboration mode, export CAD data including logical library data, such as symbols and parts; and additional library data, such as PCB models, other models, datasheets, and 3D models.

In this release, speed and resource optimizations are available including faster handling of large designs with more than 100k component instances, reduced run-time memory usage for variants yielding up to 4× speed improvement in test conditions and reduced installation size and memory footprint for standalone System Capture with no impact on the product functionality.

The DC Resistance and Topology Extraction workflows have been added to the IDA workflow list for direct access within System Capture.

Based on the target IC impedance, estimate and place decoupling capacitors at the schematic stage. A target impedance section is added to the Add Bypass Capacitors and Change Capacitor Quantity windows.

Several usability enhancements have been added in this release of system capture including full-screen canvas editing, navigation option in the search results, active item tracking, pasting images, search field available in tabs, and more.

The new subcategories are supported for ICs including Digital IC, Analog and Mixed Signal IC, DRAM, SRAM, Processors and Controllers, Memory, and Programmable Gate Arrays.

The USER_FIT parameter is now available to calculate MTBF. This parameter is supported for the FIDES standard.

The IC Pin Properties section of the Electrical Stress Settings dialog box now has separate categories for EOS and audit parameters. The EOS parameters now include amplitude (V), pulse width, time period, frequency, and delay.

All published data in an Allegro X Managed Library database, including data objects, can be imported into Pulse.

Templates for parts, manufacturers, MPNs, and symbols can be updated even after they are created, allowing adjustments to existing library objects.