Experience next generation design solutions today with the latest feature packed release of Allegro.
Allegro System Capture has enhanced power topology visualization allowing designers to run power integrity analysis, quickly build up and view the power distribution network and analyze pre- or post-layout designs from the EE cockpit.
The Delay Tune feature has been enhanced to contour each bump individually to surrounding obstacles with a single drag window. This accelerates the tuning process eliminating the need to extend each bump individually using slide.
Use the new System Capture Viewer to view the Allegro System Capture schematic in Read Only mode with the ability to navigate and search. Enable all stakeholders to review the design with no license requirements and a separate installation package.
In this release, Design Integrity includes support for creating new templates and using existing templates for interface devices, such as ICs and connectors.
The following features have been added to the pin connectivity table:
When a setup dialog box is open, the design remains visible and switches to the read-only mode. This functionality applies to the Electrical Stress, Design MTBF, Power Topology, and Device Settings windows.
Parts now be selected and navigated to via the Electrical Stress, Design MTBF, and Power Topology Settings windows. Right-click a part name and select Show in Search Results or right-click an instance and select Highlight.
A new feature to run netlist checks in DB Doctor can be used when exporting a netlist or layout. If any errors are found, a prompt appears to correct and export the design or cancel.
You can now run thermal analysis directly in the familiar Allegro X Layout Editor framework, which significantly optimizes the design process and compresses the overall design cycle.
Create a set of components and connectivity and assign a label to the set. This set is called a function overlay and can span pages and contain components and nets.
Place multiple sections of a part as an abstract component and manage pin net connectivity in a table. This hybrid design environment is convenient for analog RF devise and large pin-count designs.
The product choices dialog box now provides an option to show all older, available license strings or just the latest versions.
Analysis Model Manager (AMM) support is now available in System Capture. With AMM, you can control the default model settings, manage external model libraries, assign custom models for different types of components, and create models.
To capture the pin-based information for connectors, pin properties have been introduced in the Electrical Stress Settings dialog box for PIN_VIH, PIN_VIL, ACTIVE_LOW, INT_PU (Internal Pull up), and INT_PD (Internal Pull down).
Create a new device category and assign them to existing categories. Parts under undefined categories can now be automatically detected and assigned to the existing categories.
New audit rules are added for ICs under the Connectivity Checks category for auditing a schematic in the Design Integrity solution.
Design owners can now publish the Live BOM from Allegro X System Capture and the Pulse web dashboard. Publishing Live BOM makes the parts list available in the Unified Search filters.
System Capture and Pulse web dashboard now include an option to import a CSV file containing part details in the Append or Replace mode. Append adds only new parts from the CSV to your BOM and updates unused parts if they are in the CSV. Replace overwrites all the existing unused parts in the BOM with the new ones from the CSV file.
When uploading attachments, the versions of comments and tags can also be managed in the 24.1 release. The Attachments tab in the Pulse web dashboard helps you retain the change history and track modification of all previous attachments included in the project. This enables designers to download the older versions of attachments and edit the tags for committed versions.
When adding bypass capacitors to the schematic, you can add multiple-value capacitors to a bypass rail. The default quantity for each capacitor is 1 but can be changed for each row, allowing you to quickly perform what-if analysis.
Creating system-level designs includes the following enhancements:
Part Manager now includes the ability to cross-probe to any part instance on the canvas from a row. This helps you view the part in context of its circuitry and make a more informed part decision when selecting a replacement.
Power topology analysis properties can now be configured directly from the power topology view. This saves time and quickly rebuilds the power rails extracted from the design.
Create new parts with single or multiple pin lists repeated in multiple sections (symmetric/asymmetric parts) by copying the pin list in the flattened view of the table.
When selecting a template after launching Publish for Manufacturing application, its configured connection is displayed by default. This helps you decide what template to use before logging in.
Workflow-assisted Thermal Analysis with the ability to perform what-if analysis to change the power source from user rated or stress derived or change the placement of components on the board. In-Design thermal analysis includes the ability to view the final temperature and power of components in a tabular format and the ability to view thermal visions for each layer.
View Schematic as Read-Only with the ability to navigate and search with a lightweight separate installer and no license required.
Design metrics are now collected automatically using the design data as the design evolves. Track and evaluate project progress using charts, such as bar, line, or donut charts, to visualize changes across design versions. This includes 130 out-of-the-box metrics for the schematic, BOM, and layout in the Pulse web dashboard.
Pulse now supports secure collaboration with external design contractors, original equipment manufacturers (OEMs), and original design manufacturers (ODMs) using Cloud Identity proxy services with Zero Trust Network Access (ZTNA) deployment topology. This release provides deployment support with Microsoft Entra ID Application Proxy.
For easier adoption of software updates into your production environment when you are in the same Java stream, you can now set a system variable, CDS_JAVA_HOME, to the custom Java 11 path.
The Pulse User Management module has been upgraded to Keycloak 21.1.2 to support Javea 11. The Keycloak upgrade provides an enhanced user experience for administrators and includes new features such as paging support, streamlined identity provided configuration, and group mapping with SAML2 claims.
An audit feature is now available in Publish for Manufacturing for designers to ensure design integrity prior to publishing ECAD data and reduce data synchronization problems between PFM and the associated PLM system.
You can now publish a new component at the time of creating it within the Component dialog box. The publish functionality is also available from the component dialog box when you edit an existing component.
Multifactor authentication has been added to provide an additional layer of security and prevent unauthorized access to your account. (Available beginning in Version 23.1 ISR6)
Access control provides both an internal workspace for organizational access and an external workspace to include users outside your organization. (Available beginning in Version 23.1 ISR6)
Create region specific shared workspaces for Asia, Japan, Europe and USA. (Available beginning in Version 23.1 ISR6)
Single click action to assign default roles and access to all users in an organization. (Available beginning in Version 23.1 ISR6)
Cloud compatibility with CIS has been incorporated (Available beginning in Version 23.1 ISR6). Import and reuse existing CIS database configuration files in cloud workspaces.
Bulk upload of files directly from the File Manager UI with drag and drop functionality. Publish dialog remembers the last published workspace and the publish button is available within the component dialog box.
Predictive Analytics including part forecasting (lead time, inventory change, price change, market availability), the ability to set lookback and forecast duration to view historical data, dynamic synchronization with your design, the ability to launch LiveBOM on a local design, and duplicate and unassigned reference designator handling has been added. (Available beginning in Version 23.1 ISR6)
3DX canvas has been enhanced with all the functionalities found in the 3D Canvas and unrestricted design size. 3DX canvas can now be navigated with the keyboard using the arrow keys.
You can now use the model mapper tab to map 3D models to footprints, devices, or mechanical components. Import and export functionality allows you to export a mapping file of the existing components and their associated mapped models and import the file after editing to update the components.
Export 3DX canvas designs into the OpenUSD (Universal Scene Description) format that is needed to import into the NVIDIA Omniverse platform.
Frozen dynamic shapes can be selected to resolve all dynamic voiding DRC Errors using the Update Shape command which updates dynamic voids across the entire shape. Additional commands have been added to delete any dynamic voids inside a frozen dynamic shape, select dynamic voids, defining a void area for update.
To void shapes underneath an object (Example: to avoid coupling noise from adjacent shapes, establish impedance reference several layers down, or remove unwanted return path references), the new void adjacent layers command allows you to select objects on the canvas for which adjacent voids will be automatically generated.
Enter single-ended and differential impedance requirements directly in the cross-section editor for automatic generation of the appropriate physical constraint set for net assignment in the constraint manager.
Two new DRC-related checks minimize signal integrity impacts early in the design process without solely relying on backdrill to reduce via stubs on high-speed interfaces. These checks can also be used to validate the design during final sign-off before release to manufacturing.
Use a new check to calculate the root sum squared (RSS) length of horizontal and vertical routing, which reports a DRC error when it exceeds an acceptable threshold.
A new check is available that counts the number of times a differential pair is routed between two vias of another differential pair, using controls to check for combinations of vias, pins, or vias and pins. There is also additional control to ignore certain low-speed differential pairs, enabling routing between vias.
The Quickviews list in the visibility panel lists all placement layers in a design for quick display, with Component Reference Designators contained inside the component boundary without the need to display additional layers. This new option displays the Top and Bottom placement layers by default with the additional entries for Embedded component and Zone Placement Layers added dynamically.
Objects that can display embedded names is expanded to avoid extensive queries or the display of special layer text that may not always be readable in layout.
When routing differential pairs through a dense area, the space transition area has been improved to no longer require excessive lead-ins which results in DRC errors requiring manual cleanup. Improvements have been made to leverage the differential pair trace width and space as well as the pad geometry to calculate the appropriate pad entry that produces DRC-free and manufacturable results.
The new custom smooth option, Allow Electrical DRCs, temporarily ignores electrical constraint DRC errors so that completed routing can be optimized to the shortest, cleanest path and is ready for tuning.
The Delay Tune feature has been enhanced to contour each bump individually to surrounding obstacles with a single drag window, without the need to extend each bump individually using slide, except for final tweaks only to bring the route into spec.
Ignore No Connect (NC) nets by setting a new net property (NC_IGNORE) along with the new user preference (disable_ncnet_count_display). Nets with the NC_Ignore property are not counted in the unrouted nets/unrouted connections count and Quick Reports – Unconnected Pin Report.
Default film record automation is replaced with configuration-based film categories to intelligently generate film records.
New Acid Trap check, minimum angle with convex checks, builds upon the existing minimum angle acid trap check, which only find and verifies concave situations. The new check also finds and verifies convex situations for clines and static shapes and combinations of these two design objects as they relate to pads and vias.
The FIDES standard is now supported for real-time analysis to give better reliability results.
System Capture now supports locale language settings for Chinese and Japanese.
In addition to defining constraints at the block level, now you can define constraints on nets or pin pairs at the page level.
Filters are introduced for version metadata, layouts associated with schematics, tags, and comments. This is helpful when comparing versions or when rolling back to earlier versions. You can also edit tags assigned to previously committed versions of a design.
Project View and design view have been added to the open projects dialog box to search, filter and sort data.
New Tcl commands are added to enhance design data management in System Capture.
The thermal map generated for the board is now available as a tab within System Capture. Any analysis can be run in the thermal map tab. New icons have been added to the Thermal Floorplan results dashboard to support this integration.
RF blocks can now be imported into an existing System Capture design without affecting the design’s grid. The RF design gets imported as a read-only block if the grid settings do not match. A technology file can be directly exported from Allegro PCB Editor for CUL translation. The Cadence Unified Library Translator has many enhancements to support appending, deleting, or comparing translated libraries.
Components on the canvas can be directly added to a function. Changed parts in variants appear in a different color and alternate parts appear in italics. When rows or cells are selected, the count of the selected rows is available.
When designers want the library properties to remain in sync with the libraries or preserve overrides in the design, Part Manager flags user properties and you can replace these edited properties with the values in the library.
Expand or collapse Live BOM panels to view the graphical charts or data in more detail. Filters have been introduced to find the required information based on the specified criteria. To view part related errors and warnings, you can now click the parts in the table. Hover over the charts to see relevant parts based on their count and percentage.
Power symbols can now be replaced based on property.
Multiple pages can now be deleted in one go in the Project Explorer.
User-defined properties are now supported on the page border of the canvas. You can add, modify or delete them.
This directive controls which injected properties are to be excluded while checking for mismatched values.
Enhancements include permission-based design search results, four new sections to access required details (Project, Design, Layout, and Other), preview the schematic, view project details on the web, open linked layout versions of designs and blocks, visual indicators in search results help to identify recommended designs.
PFM is now supported in Allegro X Advanced Package Designer (APD). Administrators can specify a package as a layout source for .sip or .mcm files committed to Pusle. This enables layout engineers working in a pulse-enabled APD environment to publish ECAD data to the configured PLM system.
Publish for manufacturing provides options to extract and publish a set of metadata from Pulse to 3DEXPERIENCE to capture metadata about IC package designs in 3DEXPERIENCE for users who do not have access to the Cadence Allegro X Advanced Package Designer (APD) Application.
Support has now been added to deliver multiple files with a single utility.
A Filters option has been added to support version metadata, layouts associated with schematics, tags and comments. This allows you to compare versions or rollback to an earlier version.
Two default tags, Ready for Schematic and Ready for Layout, are available in an out-of-the-box Cadence installation when committing a design to Pulse.
Pulse administrators can customize the Live BOM summary pane by adding or removing widgets for a tailored view of the BOM summary. Changes can be published for all users connected to the server.
The previous Mandatory Utilities section is now revamped and renamed as Utility Selection Rules. In these settings, administrators can define which utilities must be run when publishing to a PLM System and define the default utilities for data publishing to a PLM system.
Enhancements to the 3DEXPERIENCE connector include a product number search enabling you to search by string, storing PLM revisions in the pulse project, assigning number filtering, and automatically filtering board numbers based on PLM structure to ensure that the assembly-board relationship configured in the PLM system guides you towards the proper board selection in PFM.
Live BOM updates include the following:
The Unified search interface has been updated to include permission-based design search results. The User interface has been improved to include four new sections: Project, Design, Layout and other as well as including the ability to preview the schematic, view project details on the web, and open linked layout version controls for the design and blocks. Design rules can now be configured to include visual indicators in the search results to help users identify and select recommended designs.
