Allegro/OrCAD/PSpice Version History

PSpice now allows modeling of nonlinear behavior for passive devices such as resistors, capacitors, and inductors using mathematical functions. Nonlinear devices are available under the Ideal Devices > Passive Category in the Component Explorer panel.

PSpice A/D now supports the following step, mathematical, and random functions to model the electrical behavior of a circuit:

• SMSTP(X)
• STPA(X)
• BUF(X)
• DNLIM(LOWERLIMIT,X,SOFTNESS)
• HYPOT(X,Y), LENGTH(X,Y)
• INT(X), TRUNC(X)
• INV(X)
• UPLIM(X, UPPERLIMIT,SOFTNESS)
• URAMP(X)
• NRAND(X, S)
• ZRAND(X, S)
• RANDOM(X, S)
• ZRANDOM(X, S)
• ROUND(X)
• WHITE(X, S)

PSpice now supports advanced built-in functions to model memristors. The new models are included in the memristor.olb library.

Transient sources for standard CI 210 have been added, which test AC immunity from continuous disturbances. PSpice now supports the following additional ISO 16750-2 transient sources used for automotive applications for 12V and 24V systems:

• 9.1 Single Line Interruption
• 6.4 Load Dump Without Centralized Load Dump Suppression – Test A
• 6.4 Load Dump With Centralized Load Dump Suppression – Test B

GaN MOSFET models are now available and can be accessed from the Component Explorer panel under Discrete.

PSpice now supports sweeping of components models to perform design exploration with different models in a single simulation run. Evaluate different models for a given base model and compare them to see how the circuit behavior changes for different models.

The .MEASURE commands can now be used to evaluate complex expressions that include node voltages and current. Additionally, different parameters, including voltage, current, global parameters, and temperature; can be swept.

OrCAD X PSpice Designer and OrCAD X PSpice Designer Plus now have access to OrCAD X Cloud.

This release introduces positive masks, an enhancement for mask layer visualization and manufacturability. Traditionally, mask layers are negative, where the visible objects on the canvas represent openings in the mask. The traditional approach requires designers to mentally invert the image to understand the manufactured outcome. Interpreting these negative mask visuals as positive during 3D rendering or manufacturability checks can be counterintuitive and error-prone, adding complexity to the design and review process.

With this new feature, mask layers can be treated as positive, making it easier to visualize and verify mask shapes. A new option, Positive Mask, has been added to the Cross-section Editor. When enabled, a dynamic shape is generated on a new Positive Mask class, representing the mask layer. Openings in this dynamic shape use the same model as dynamic copper shapes, however, voiding is performed using the traditional negative mask pads in padstacks and objects on mask subclasses, which are typically exported for manufacturing.

This update modernizes the way text is managed in PCB designs, aligning the tool with industry-standard applications. You now have the flexibility to choose from a wide range of fonts that reflect personal or corporate branding while also improving the visual clarity and consistency of design documentation. In addition to standard fonts, the Mooretronics font is also supported within layout editors.

The docked Constraint Manager is a new Constraints panel that simplifies the process of assigning and visualizing constraints directly from the Layout Editor user interface. It presents constraints in a graphical format and organizes them under Basic and Advanced modes. Constraints can be controlled at the group level rather than the net level by assigning constraint sets at the net group, net class, and differential pair levels within the Object Hierarchy panel.

The Search panel is a new dockable panel that allows you to instantly query database objects and cross-probe them from the canvas or panel to find information and objects quickly. This provides on-demand content loading to reduce memory usage and improve performance, real-time updates to ensure you have access to the latest information, and custom column filtering to allow columns to be rearranged as needed.

Smart Search is a new search engine that generates predictions based on entered keywords or questions to find the information you need to complete a task directly in the layout. This feature is useful when modifying the design by applying object properties or setting user preferences while working on it.

A new configuration-based solution defines all required data exports and manages export parameters in a single dialog box. It eliminates the need to explore different areas of the layout editor to produce manufacturing exports.

The enhanced pin delay import feature provides auto-detection, column and cell validation, and the ability to adjust column categories and values directly within the dialog box without modifying the source CSV file. The enhanced functionality queries the database to flag missing Reference Designator and Pin Number combinations in the design and allows selective import by deactivating rows and columns as required.

In this release, Cadence continues to expand the capabilities of 3DX Canvas, helping designers visualize their PCB layouts in a highly realistic 3D environment before sending the layouts to manufacturing. 3DX Canvas has been enhanced to selectively display and incrementally add objects to the 3DX Canvas, making the environment far more interactive and efficient. You can now highlight selected objects in the 3DX canvas from the PCB, cross-probe objects, and adjust the 3D view automatically.

OrCAD X PCB Editor has several performance enhancements added included DRCs, import and export of design data, placement and interactive placement, routing and interactive routing, dynamic shapes, padstack refresh, 3D view, and in-design analysis.

The following new SKILL functions have been added:

• axlGetPreselectSet: Returns a list of the currently preselected database objects.
• axlGetPreselectSetCount: Returns the count of the number of objects in the preselection set.
• axlXSectionGetDrillDirection: Returns a symbol indicating the drill direction for the layer pair.
• axlSetRKSPCTolerance: Sets the allowable tolerance for a route keepout based on spacing domain rules.
• axlGetRKSPCTolerance: Returns the route keepout or route keepin-based tolerance value.
• axlDumpDRCModelinXML: Dumps DRCs in a particular category in an XML file.
• axlPulseGetDesignUrl: Returns the Pulse design URL.
• axlGetBends: Returns a list of bend names.
• axlGetBendInnerRadius: Returns the inner radius value for a bend name.
• axlSetBendInnerRadius: Sets the inner radius value for a bend name.
• axlFormIntroDoc: Describes control types and functions for creating interactive forms.
• axlImportDegassingParams: Imports degassing parameters from an Excel file.
• axlImportMetalFillParams: Imports metal fill parameters from an Excel file.
• axlDBChangeText: Modifies the characteristics of a text string in the layout.
• axlDBChangeTextStyle: Modifies an existing text style using the specified text style parameters.
• axlDBGetTextStyleCharacteristics: Returns the characteristics of a text style object.
• axlDBGetTextStyle: Returns the text style information.

The following SKILL functions have been modified:

• axlPadOnLayer: Tests if a pad is present on an etch layer.
• axlCanvasPrintToPDF: Saves the design file in PDF form.
• axlDBControl: Inquires or sets the value of a special database control.
• axlTriggerSet: Allows registering interest in events that occur in the database.
• axlParamShapeDoc: Supports access to the dynamic, static, and layer parameter records.
• axlDBCreateText: Creates a text string.
• axlDBCreatePin: Adds a pin.
• cmxlExportFile: Exports Constraint Manager object information to a file.
• cmxlImportFile: Imports a file to update a Constraint Manager object.
• cmxlFindOrCreateQBR: Queries a database object and returns an object if it exists or creates it if it does not.

The Reports panel is a new dockable panel that automatically loads selected Quick Reports for easier review and canvas navigation. This panel eliminates the need to manage a separate floating report viewer for the Shape Islands Report, Unassigned Shapes Report, Missing Teardrops Report, Missing Tapers Report, and the Dangling Traces, Vias, and Antenna report.

25.1 introduces a new dialog box, Differential Pair Automatic Setup, which provides a unified solution for generating differential pairs. This dialog box combines all unique features in the existing solutions available within and outside the Constraint Manager and simplifies the process of generating differential pairs.

The metal density scan command, used to perform metal density analysis of design layers, is enhanced for performance. The command also provides additional metal density checks and options to meet manufacturing requirements such as minimum/maximum metal density across layers and metal density difference between two layers.

Support for TrueType fonts has been introduced to OrCAD X Presto. This feature provides more control over the appearance of layout designs and allows users to incorporate preferred fonts. Styles can also be created to define specific fonts for particular uses, such as silkscreen texts. In addition to standard fonts, the Mooretronics font is also supported within layout editors. This font provides many standard symbols used in PCB design. Install this font locally to use it seamlessly in your designs.

Pad directories can be modified directly within the design environment in the Property panel. Select a pad and change its properties without having to launch the Padstack Editor or navigate multiple menus.

The Import Pin Delay feature allows pin delay to be imported from various file formats, such as Excel files, Allegro Constraint compiler files, and existing pin delay formats.

The Auto Define Differential Pairs feature simplifies the process of defining differential pairs in a PCB design, saving time and effort. The functionality is accessible from the top-level menu and supports default differential pair patterns.

The Export Libraries feature extracts libraries from translated third-party designs, making it easier to reuse libraries in OrCAD X Presto designs.

LiveDoc now provides the ability to add assembly notes and instructions as well as using variables in title blocks and assembly notes. The variable values can be defined in the Property panel of LiveDoc and update globally across the document.

Web-based PCB design review allows all stack holders to collaborate and review the PCB design. Efficiently review and add markups and comments to PCB designs in real-time, facilitating efficient collaboration and reducing errors.

OrCAD X Cloud can be used to share workspaces directly via the Web, making collaboration with team members and stakeholders easier. This feature enables seamless sharing of design data, eliminating the need for manual file transfers and ensuring that everyone has access to the latest design information.

The exploration and analysis feature in OrCAD X Presto, powered by Sigrity analysis technology, brings signal integrity and power integrity analysis capabilities directly to the design engineer and layout designer. Integrated access allows users to leverage their Sigrity Aurora licenses and perform crosstalk analysis, reflection analysis, return path analysis, and decoupling capacitor placement analysis directly in OrCAD X Presto canvas.

Review a schematic design using comments and markups. Mark any area in the design canvas using rectangular or arrow markups and add text comments in for efficient design reviews.

Find objects by parts, pins, nets, text, class, with additional search criteria for object properties and display properties. Efficiently replace values using the new replace dialog box.

The settings of a design template can now be saved as a .dtp file and loaded to reuse in a design. Save and load templates for later reuse in schematic designs allowing you to quickly configure design properties such as text font and size.

View and review schematics directly within the Cloud environment. This feature provides real-time collaboration and feedback, streamlining the design review process. Add markups and comments on schematics to ensure all stakeholders are aligned.

Share workspaces directly via the Web, making collaboration with team members and stakeholders easier. This feature enables seamless sharing of design data, eliminating the need for manual file transfers and ensuring that everyone has access to the latest design information.

With this unified cockpit designers can seamlessly edit, plan, and modify the PCB layout with the easy-to-use X Layout platform directly in System Capture. This change enhances collaboration between the schematic and PCB layout and incorporates additional features such as preferences and constraints to help communicate design intent upfront.

The System Capture system-level design workflow is upgraded to improve complex multi-board project handling and design reusability. Key enhanced features include:

• Multi-Page Logical Board Placement: You can now place parts of the same logical board on different schematic pages and use the same logical block multiple times in other parts of the design.
• Ignore Subsystem Option: A context menu, Ignore Subsystem, has been introduced to exclude specific subsystems from system-level connectivity checks and report generation.

System Capture now supports generating navigation link reports, also called cross-references or CRef reports. Reports for Nets by Page, Base Net, Pin Cross-References, CRef parts, and Synonyms can now be created to be viewed in the schematic or exported as text files. These reports provide detailed connectivity and component cross-referencing insights to help quickly analyze design relationships and locate elements across pages and blocks.

System Capture designs now handle cells with the same names across libraries. To support this enhancement, physical part names are modified to avoid conflicts.

SnapMagic is now available in Unified Search to expand the list of available components. The SnapMagic parts database can be accessed without leaving System Capture.

You can now run electrical stress analysis on a specific device such as an IC, connector, DC-DC/LDO, or mechanical device.

A new workflow to streamline electrical stress analysis has been introduced. The EOS workflow can be accessed under View > Analysis Workflows > Electrical Stress.

Separate dashboards to analyze pre-layout and post-layout power topology analysis results are now available.

The Pulse web dashboard now supports design variants. To choose a variant, open the Schematic tab and select the Variant dropdown. This enhancement allows designers to switch between variants and easily review or download them.

System Capture and the Pulse web dashboard have enhanced design search and version control capabilities. These include:

• • • • • • • • • The MATCHES column shows BOM-Only Components and Variant Components for design search results.
                • Version control for designs and blocks is available in the Design tab of Unified Search.
                • A new filter called Reuse From has been introduced. This filter shows the source of the design block that is reused.
                • A new Reuse section has been added to the project Details tab. This section provides quick access to details of an imported block. This section shows key information for the block plus version information.
                • The Version Control window now supports version management at the block and page levels.

With the new Local Library feature, create and manage libraries directly on your computer. With this new feature, a pulse server connection is not required, all symbols are edited and stored locally with complete formatting support. Anyone can author these local libraries and no role-based restrictions apply. Additionally, custom shapes from managed libraries can be reused and importing pin lists for faster symbol creation is available.

Validation rules now offer enhanced customization for system-defined rules, with the ability to specify the object stages in which they run, such as Validate, Check-in, Pre-Release, and Release. User-defined rules can now be created for all library object types, beyond libraries, parts, symbols, and footprints.

Multi-package support is now available for library symbols. Multi-packages are symbols with the same number of pins but different pin configurations. A sectioned symbol, such as a 4-pin symbol split into four single-pin sections, is also considered a package. This new feature helps to manage different package variants of the same component.

In the Collaboration mode, export CAD data including logical library data, such as symbols and parts; and additional library data, such as PCB models, other models, datasheets, and 3D models.

In this release, speed and resource optimizations are available including faster handling of large designs with more than 100k component instances, reduced run-time memory usage for variants yielding up to 4× speed improvement in test conditions and reduced installation size and memory footprint for standalone System Capture with no impact on the product functionality.

The DC Resistance and Topology Extraction workflows have been added to the IDA workflow list for direct access within System Capture.

Based on the target IC impedance, estimate and place decoupling capacitors at the schematic stage. A target impedance section is added to the Add Bypass Capacitors and Change Capacitor Quantity windows.

Several usability enhancements have been added in this release of system capture including full-screen canvas editing, navigation option in the search results, active item tracking, pasting images, search field available in tabs, and more.

The new subcategories are supported for ICs including Digital IC, Analog and Mixed Signal IC, DRAM, SRAM, Processors and Controllers, Memory, and Programmable Gate Arrays.

The USER_FIT parameter is now available to calculate MTBF. This parameter is supported for the FIDES standard.

The IC Pin Properties section of the Electrical Stress Settings dialog box now has separate categories for EOS and audit parameters. The EOS parameters now include amplitude (V), pulse width, time period, frequency, and delay.

All published data in an Allegro X Managed Library database, including data objects, can be imported into Pulse.

Templates for parts, manufacturers, MPNs, and symbols can be updated even after they are created, allowing adjustments to existing library objects.

Prior to release 25.1, backed-up Pulse data was saved as individual Zip files in the Pulse home. To speed up the restore process, the checkpoints (backups) are now stored in folders rather than Zip files.

From release 25.1 onward, support for Design Entry HDL (DE-HDL) will no longer be available, and DE-HDL design flows in Allegro EDM are no longer supported.

A new solution, Allegro X Managed Library (AML), for centralized library authoring, data management, and enterprise collaboration has been introduced in this release for Allegro System Capture. AML standardizes workflows, ensures data consistency, and streamlines the PCB design process in a scalable environment integrated with Pulse.

In this release, Design Integrity includes support for creating new templates and using existing templates for interface devices, such as ICs and connectors.

The following features have been added to the pin connectivity table:

• Import or export pin lists for a component
• Search and filter components
• Section support in the connectivity table
• Easy identification of multiple pins connected to the same net
• Clear visual distinction between editable and non-editable pin connections
• Flagging of mismatches in pin numbers when importing pin lists

When a setup dialog box is open, the design remains visible and switches to the read-only mode. This functionality applies to the Electrical Stress, Design MTBF, Power Topology, and Device Settings windows.

Parts now be selected and navigated to via the Electrical Stress, Design MTBF, and Power Topology Settings windows. Right-click a part name and select Show in Search Results or right-click an instance and select Highlight.

A new feature to run netlist checks in DB Doctor can be used when exporting a netlist or layout. If any errors are found, a prompt appears to correct and export the design or cancel.

You can now run thermal analysis directly in the familiar Allegro X Layout Editor framework, which significantly optimizes the design process and compresses the overall design cycle.