Allegro PCB Platform Release History

Cutting-Edge Technology Requires Constant Innovation

Cadence Allegro is a driving force in the PCB design industry and is constantly evolving to meet the demands of today’s technology. Cadence has been accelerating the rate of innovation and delivering a stream of updates and product enhancements to users so designers can easily keep up with the constant pace of change. The release history below provides insight into industry-first capabilities such as advanced layout and routing, intelligent design for manufacturing, chip on board, tabbed routing, intuitive high-speed design, dynamic collaboration, and more.

Version Notes:

  • Cadence provides bi-weekly updates to its products to fix issues and defects as quickly as possible for customers
  • New functionality is also delivered through quarterly incremental releases (QIRs).
  • Customers are encouraged to stay on the latest update within a release as they will not only get access to any fixes but will also have access to new features (as described below) available through the QIR stream.
Related Links

Release History:

Version 23.1

Products Covered: Allegro X Layout Editors | System Capture | Pulse

Allegro X Release. Innovative design platform focusing on providing a cohesive and comprehensive solution for all design requirements.

Allegro X Layout Editors

23.1

  • Enhanced Documentation. Cadence Doc Assistant presents help content as individual easy-to-read topics and has improved the speed and relevance of search capabilities.
  • Counterbore/Countersink. Define secondary drill definitions on either the primary or secondary side.
  • Microvia Slot. Expanded the capability of microvia drill support beyond circle and square-plated holes to include microvia slot. This allows rectangular or oval-plated slots while following standard microvia constraints in the design.
  • Drilled Hole Padstack Definitions. Drilled hole fields for circle and square holes as well as round slot fields for rectangle and oval shot holes have been added for accurate unit-controlled values of the drill hole size before plating and tolerances.
  • Multi-Drill. Pitch values for rows and columns can now be defined to calculate the spacing automatically for a multi-drill.
  • Freeze/Unfreeze Dynamic Shapes. When dynamic shapes need to remain constant to protect critically circuitry and maintain design intent, suspend or freeze dynamic voiding instead of converting to static shapes. Once frozen, new objects entering a shape will not void and will generate a DRC error.
  • Zone Adherence for Symbol Pins. Components placed in a zone with some of the pins protruding into another zone can cause buried or floating pins. Easily check to verify that all pin pads of a component exist on the same placement layer.
  • Nested Zone Support. Designate stackup differences in particular areas of your rigid-flex designs by defining one zone inside another for scenarios where one shape needs to be surrounded by another.
  • Updated Zone Boundary Editing. Zone modifications can now be performed without activating Shape Edit Application Mode.
  • Fill-In Materials. Define the fill-in material for multi-layer PCBs to account for the different dielectric constants that affect the electrical characteristics of conductors running across the dielectric​.
  • Design Review and Markup. Facilitate a collaborative design review environment with the ability to markup and comment design feedback directly in the PCB canvas. Markups are stored in the design database, streamlining the design review process. 
  • 3D Model Mapper. Automatic mapping and fine-tuning of the x, y, and z placement provides efficient methods for mapping 3D models to the footprint directly in the library.
  • 3D Model Export Support. Export the complete 3D representation of the entire design or individual objects as STEP, IGES, ACIS or a PDF.
  • Updated Dimension Line Width. Define dimension parameters to apply a line width globally for all dimensions.
  • Z-Copy Enhancements. Define the net during Z-copy to copy etch shapes to other layers. Incorporate a subclass wildcard to copy the shape to multiple layers.
  • Place Replicate Enhancements. A new delete option will remove routing from the previous module for components that are part of another module.
  • Netlist Import Enhancements. Reuse device files and component definitions that are currently in the design when loading an updated netlist.
  • Net Short Report. New net short properties report is available to easily find all the objects in the design with the Net short property to verify the nets being shorted.
  • Creepage and Clearance Checking. New high-voltage constraint checks to verify creepage and clearance rules. Design Rule check system recognizes non-plated slots between two high-voltage objects and recalculates creepage and clearance. Creepage and clearance vision provides graphical feedback with color-coding directly on the canvas for efficient analysis.
  • Power Delivery Generation. Quickly generate power planes for a section of the design of the entire design based on pin placement, boundary, or design outline. Review power plane escape and adjust placement or constraints to improve power connections.
  • Signal Integrity Optimization in CPU Pin-Field. A new routing tab utilizing complex shapes that follow serpentine pattern contouring to pins and vias allows you to maximize tab size and reduce impedance when routing through CPU pin-fields.

OrCAD X Capture CIS

23.1

  • Enhanced Help Documentation. Cadence Doc Assistant presents help content as individual easy-to-read topics and has improved the speed and relevance of search capabilities. New documentation has been provided for library and part management, part authoring, and more.
  • Enhanced Component Explorer. Access all the library sources along with complete part details in a unified view. The intuitive user interface provides access to various libraries supplied by Cadence, PSpice libraries and models, and external providers.
  • Integration with Content Providers. A new content provider has been integrated into the unified CIS environment. In addition to Ultra Librarian and SamacSys, SnapEDA can now be accessed directly through the schematic.
  • Integrated Part Authoring. Create new components from scratch using available libraries or existing parts from content providers. An easy-to-use dialog box lets you easily configure a description, category, logical symbol, footprint information, PSpice models, and electrical specifications. Incorporate lifecycle tatus, manufacturing part numbers, and more.
  • Part Template Creation. Quickly create parts from templates containing verified symbols, footprints, models and properties and organize the parts in the workspace efficiently.
  • Teams and Workspace Support.  OrCAD X provides a new collaborative development environment to create shared workspaces containing work-in-progress components, projects, libraries, and design files. Create multiple workspaces for different projects and user needs. Share workspaces, define user access and roles to efficiently collaborate with team members.
  • LiveBOM. LiveBOM is a dynamic bill of materials (BOM) that is generated using up-to-date supply chain data with zero configuration. The rich UI provides live part status from cloud libraries including real-time component availability, price data, alternative parts, life cycle status, dynamic part information and more.

System Capture

23.1

  • Thermal Analysis and Celsius Integration. Generate a thermal floorplan to estimate the life of the PCB design and improve placement of components early in the design cycle.
  • Topology Workbench Integration. Launch Topology Workbench directly from the System Capture canvas to analyze the signal integrity of high-speed nets at the schematic, floorplan, and layout stages.
  • Mean Time Between Failures (MTBF) Analysis. Perform MTBF analysis on a design to estimate the performance and safety of electrical, mechanical, and electro-mechanical parts for Allegro X Designer and above.
  • Power Topology Analysis. Enable the verification of all the components in a design in the early stages. Set up a power distribution network on the schematic to estimate the DC power consumption by components in the PCB design for Allegro X Designer and above.
  • Adding Parts to Libraries. In addition to adding parts from external content providers directly into a design, Unified search now supports adding parts to libraries from SamacSys or Ultra Librarian.
  • Library Authoring Enhancements. Create a new template library, create categories and subcategories in libraries to improve component searching, edit multiple parts in a spreadsheet and enhanced part validation improves the library authoring experience.
  • Integration with AWR. Integration to AWR Microwave Office and Allegro PCB Design applications provide a way to create complex PCBs with RF design. Enhancements to this integration include a single impot from AWR Microwave Office into System Capture and more.
  • Variant Editor Enhancements. May enhancements have been added to efficiently complete variant designs including creating function groups, defining alternate parts, defining variants, and the ability to switch to variant views.
  • PDF/A Support. System Capture now offers long-term archiving ability with the PDF/A format in addition to the PDF and SmartPDF formats.

Pulse

23.1

  • Bi-Directional Synchronization with Allegro X EDM and PTC Windchill. Allegro X EDM library parts can be updated with changes in the Windchill part data and vice versa.
  • Dashboard Enhancements. Enhancements to the Pulse Web Dashboard are available to single-user and multi-user environments of System Capture. Enhancements include additional filters, save column visibility, project-specific URL for bookmarking, and more.
  • Version Control. Easily compare two versions of a design to determine the correct path forward as a team. Compare the latest revision or the previously committed version of the design.
  • Offline mode. Users in a multi-user environment can disconnect from the Allegro Pulse server and work in the offline mode, ensuring uninterrupted work using parts in the design cache.

Version History

Version 22.1

Products Covered: Allegro Layout Editors | System Capture | Pulse

Allegro Layout Editors

22.1

  • Topology Editor. A non-analysis version of Topology Workbench for constraint capture is now included. 
  • On-Canvas Structure Update and Variant Creation. When reusing structures multiple times, easily update one instance and push the changes to all instances. 
  • Converting Shapes, Vias, and Pins. Easily convert objects and create or replace an object with a padstack directly on the canvas. 
  • Dimensioning Update. Easily make changes to a dimension without having to delete and regenerate it. 
  • Route Keepout Exception. Easily locate stacked vias and flag them with DRC markers in restricted areas. 
  • Performance Enhancements. Enhancements include better performance on designs with a large number of DRCs, faster update to smooth, better move performance, better performance for shape parameter per layer override, capping of command window messages, and faster DRC checking on designs with negative layers. 
  • Expanded GPU Support. GPU support now includes modern discrete or integrated GPUs from Intel and AMD. Enhancements to NVIDIA GPUs include performance gain in panning and zooming and augmented quality of display. 
  • Normalized Forms for High Resolution Displays. Easily specify a scaling factor to normalize forms that are partially cut off due to display scaling in devices with 4k or higher resolution. 
  • Parameterized High-Speed Structures. Faster structure creation for parameterized high-speed structures by leveraging information from other areas and extracting information from selected differential pair transitions (High-Speed Option Only). 
  • Differential Pair Vias Replaced by Structures. Replace via with structure has been updated to accept structures that do not contain pad entry or exit traces maintaining current routing and delay matching (High-Speed Option Only).

System Capture

22.1

  • Performance Enhancements. Performance and response time has been improved for opening and saving designs, wiring, and canvas selection. 
  • Displaying Base Net Indicators. Configure System Capture to show the winning or base net on the canvas when multiple nets are aliased. 
  • Prefix and Suffix Extended to Physical Net Names. Specify a prefix or suffix for blocks in hierarchical designs. This suffix or prefix is automatically applied to the physical net names for nets and buses. 
  • Block Printing Support. Blocks and pages can be excluded from printing. 
  • Support for Properties on Page Borders. Page border symbols and properties on page borders are now brought in as properties when designs are migrated from DE-HDL. 
  • Open Projects as Read Only.  To avoid accidental editing of designs, especially in a team design environment, lock a design block or page to enable a read-only status and watermark. 
  • Finding and Replacing Special Symbols. Find and replace feature is now enhanced to replace special symbols such as power, ground, or ports. 
  • Controlling Signal Name Copy and Assignment. Define the default behavior for wire name assignment and display settings when wires are connected to a power source or copying circuitry. 
  • Reference Designator Preservation. For multi-section instances or split instances, all sections are processed in a single transaction, enabling reference designator preservation. 
  • Automatic Purging of Bus Bits. In hierarchical blogs where the number of bits were reduced, automatically purge the deleted bus bits. 
  • Connector Pin Assignment. Select a group of components on the schematic canvas and assign pin numbers based on data from the part definition when working with single-pin multi-selection components. 
  • Programmable Parts in Variants. Specify a part code and add a preferred part regardless of the availability of parts in project libraries. Add this preferred part for any variant using a placeholder part number or browse though available parts to choose one. 
  • Visual Cues for DNI Components. Do Not Install (DNI) components in the base design can be indicated with a cross over the component. 
  • Port/Pin Assignment Color Coding. Quickly identify the nets that are perfect matches or partial matches in the Port/Pin Assignment dialog box with color coding. 
  • Printing System-Level Designs. Print system -level designs in all print formats including PDF and Smart PDF. 
  • .MCM File Support. Link the .MCM files from ADP Plus and Allegro System Capture schematic to ensure your project stays in sync. 
  • Library Authoring Enhancements. Edit Allegro DE-HDL libraries directly within System Capture and launch OrCAD Libraries to create or edit OLB schematic libraries. 
  • New Audit Rules in Design Integrity. Improve design creation and quality with additional rules including connectivity checks for MISO and MOSI pins, ref des visibility checks, fiducial checks, test pad checks, and more. 
  • Customization using TCL and Directives. Updated Tcl commands and new directives to improve customization.

Pulse

22.1

  • Pulse as a Layout Source. Define a single source for a layout design within pulse to generate all outputs to Publish for Manufacturing.

Version History

Version 17.4

Products Covered: Allegro Layout Editors | Capture | Allegro Design Entry HDL

Allegro Layout Editors

QIR 3

  • Dynamic Shape Performance Enhancements. Fast mode for dynamic shapes has been improved and significantly improves dynamic shape performance. 
  • GPU Acceleration Rendering. Leverage GPU in Allegro Layout Editors to improve response time during panning and zooming, toggling layers, and render quality. 
  • DesignTrue DFM Enhancements. Improvements include DFF Mask Rule Additions (via and SMD pad overlapping soldermasks), updated calculations for aspect ratio and line-based checks for fillets. DFM Wizard Enhancements to support DFF and DFA templates for copper features, copper spacing, DFA spacing, and component leads. Navigation improvements for the DRC Browser and the ability to waive DRC by group select. Component Lead geometry can now be displayed with control in the visibility pane. 
  • Return Path DRC. Updated to include shape void and plane edge checks to verify trace coverage by identifying overhang conditions and ensuring appropriate plane overlap is present. 
  • Parameterized High-Speed Structures. Easily enter parameters by selecting differential pair vias on the canvas to build a replacement structure for pre-existing routing. Includes five pre-defined geometries: rings, owl, oval, rectangle, and goggles. 
  • Symphony Team Design. Improvements have been made to via structure support, in-session component placement usability and database sharing usability. 
  • 3D Canvas Updates. Isometric view has been added for the bottom side of the board. Other updates include realistic plating thickness, increased model realism, and secondary model support. 
  • Reuse Module Enhancement. Dynamic shapes are automatically converted to static shapes to ensure consistent voiding. Modules applied to the design remain locked to avoid accidental modification. Addition of copper planes, constraint regions and text notes within the module file. Quickly swap a placed reuse module with a different variant in one or multiple locations. 
  • Miscellaneous Enhancements. Multi-pin scribble support when routing, align vias horizontally or vertically to improve routing and plane coverage.

QIR 2

  • Dynamic Shape Enhancements. A new dialog provides a quick way to define layer specific shape parameters. Enhanced performance for dynamic shapes with dynamic fill mode “fast” providing a fast-incremental update to dynamic shapes during interactive operations (Slide, Add Connect, discrete Moves, etc.). 
  • 3D Canvas Updates. 3D mapper now a part of 3D canvas, replacing Allegro (2D) menu. Simplified use model and GUI enhancements. Improved accuracy of collision detection and distance measurements. Additional support for mapping native CAD models (Parasolid, Siemens NX, CREO, SOLIDWORKS). 
  • DesignTrue DFM Enhancements. DesignTrue DFM Enhancements including Enable/Disable Switch for on-line DFM checks, Global Manufacturing Tolerance and Tented Via List Enhancements(top tented via list and Bottom via list). DesignTrue DFM Rule Aggregator combines DFM rules and produces a set of rules with the common denominator based on the most conservative values. 
  • EDMD (IDX) 4.0 Support. Bend sequence ordering, Geometry use identification, primary pin identification, and time stamps. 
  • IPC-2581 Revision C Support. Additional support for rigid flex (bend detail and stack-up profiles), Countersink/counterbore, square drill features, net shorts, and impedance specifications and nets. 
  • Allegro PCB Symphony Team Design. Now Symphony clients can place components directly from the placement list onto the canvas transferring the symbol data to the Symphony server database with In-session component placement. 
  • Allegro Constraint Compiler. Enhancements include improved usability and import of CSV Constraint Tables and XML Constraint Data Set. 
  • Parameterized High-Speed Structures. This prototype solution generates high-speed structures based on parameters. 
  • True Wafer-Level Chip Scale Package Design Support. The Cadence® Allegro® Package Designer Plus Silicon Layout option works with Cadence Physical Verification System (PVS) to deliver flexible silicon substrate and advanced wafer-level packaging (WLP) design capabilities. It offers process development kit (PDK)-driven design rule checking (DRC), density modification and assessment, connectivity verification, and mask artwork signoff. Therefore, the solution is suitable for designs based on emerging silicon and wafer-based packaging methodologies. 
  • Push Connectivity. Now, use the Logic – Push Connectivity (push connectivity) command to push the net of selected pins to all physically connected objects. 
  • Identifying Same-Layer Shorts and Step Coverage Problems Using Serpentine and Comb Structures. Now perform packaging test structure checks for physical opens and shorts in pattern by creating a Serpentine and Comb structure from a set of given parameters.

QIR 1

  • In-Design Analysis: New Flow and Enhancements. Allegro® In-Design Analysis environment blends the best of Allegro® and Sigrity™ technologies to provide analysis and checking capability entirely within the PCB Editor framework for Impedance, Coupling, Crosstalk, Reflection, Return Path and IR Drop. PowerTree files are no longer needed for IR Drop analysis with the ability to define VRM’s directly within the design workflow. 
  • Allegro Constraint Compiler. Support for new types of constraints such as a new table to define Routing Sections within a net or XNet for assignment of Physical, Spacing, and Electrical constraints in an ObjectRule Table. 
  • Allegro Data Management (Version on Commit). Version control features are available as an unsupported prototype within Allegro® PCB Editor and Allegro® Package Designer Plus. Native version control allows you to capture versioned snapshots of a design throughout the design process and provides an easy way for you to reference or revert to a previous version of the design. 
  • 3D Canvas Update. Filter dialog upon 3D Canvas activation to select what layers to visualize in 3D Canvas. Net information (names, type, properties, and so on) is imported into 3D Canvas and the new Nets pane allows you to control how to visualize the nets in 3D Canvas. Dim and Vanish highlighting modes for component selection. 
  • Allegro ECAD-MCAD Library Creator Update. Package Templates have been re-organized for easier selection, Rule Editing has been simplified, and manual footprint creation has been expanded with improved Boolean operations involving path and area geometries. 
  • DesignTrue DFM: New Stack Microvia over Core Via Rules. The new rules manage the number of microvias stacked over a core via, and alignment tolerance from center-to-center of microvia to core via and microvia to microvia. These checks help avoid microvia barrel cracking and via delamination during the entire fabrication process. 
  • Miscellaneous Updates. Custom Icon support for toolbars allows users to add user-selected icons to commands when customizing toolbars. In the Find by Query dialog, a new attribute Width has been added for Lines.

17.4

  • 17.2 Database Compatibility Mode. Open a 16.6 or 17.2 database in release 17.4-2019 and work on it without saving it in the new 17.4 database format. 
  • Symphony Team Design Option. Connect to a Symphony session using an Allegro® Physical Viewer Plus product license to review and mark up the design actively being worked on and not a stale copy. 
  • Hierarchical Route and Via Keepouts. Define keepout by layer type and location using the additional Route and Via Keepout subclasses that have been added to Symbol Editor. 
  • Allegro Constraint Compiler. ACC is a mechanism to inject constraints, at the interface level, with automatic translation of design constraints from an external source directly into Constraint Manager. 
  • IPC 2581 Spec Properties. The IPC-2581 format allows the inclusion of descriptive details that may be attached to specific objects, such as assembly instructions and/or fabrication notes typically displayed within a Fabrication or Assembly drawing. 
  • Mask Defined Pin Annular Ring Check. A new Mask Defined Pad check has been added to the Design for Manufacturing Annular Ring checks and the DesignTrue DFM Wizard template file. 
  • Via Array Update. Addition of a singular array command for adding, updating, and deleting many different array types. On screen dynamics provide you control and feedback by letting you dynamically adjust arrays before placing them. 
  • Contour Routing Update. Enhanced Contour behavior is now the default contouring method as well as additional spacing controls and full constraint region support. 
  • Via Structure Update. A single unified Create Structure form combines the previous Standard, High Speed, and L-Comp forms into one easy-to-use form while also adding descriptions, walkthrough guides and graphics. 
  • 3D Canvas Update. Usability improvements including 3D cutting plane updates, mechanical symbol transparency, Symbol Representation Using DFA_Bound Shapes, and unplated holes in footprints. Pastemask can also be accounted for during 3D models placement.

OrCAD Capture

QIR 3

  • Fully Integrated PCB Viewer. Access the PCB viewer directly from OrCAD Capture and cross-probe between schematic and PCB without needing a PCB license. 
  • CIS BOM Variant. Support for hyphens and underscore in BOM Variant names. 
  • Occurrence Part Update. copy-paste occurrence-based parts across the design. Occurrence properties of selected instance are preserved and copied in the new design. 
  • Access to TI Libraries. Access additional Texas Instrument Libraries from OrCAD Capture including 5000 TI-PSpice Models across 100 unique model categories and as many as 4000 test circuits.

QIR 2

  • Design Sync Updates: Dedicated actions for updating schematic and layout individually. 
  • Schematic Print Updates. Increase schematic PDF readability with the ability to set the schematic print theme independent of the canvas theme.

QIR 1

  • New OrCAD Capture Start Page. After installing QIR 1, as you launch OrCAD Capture, you will see a renewed, content-rich, and reorganized Start Page. It has been designed for you to easily access a variety of information and projects. From this page, you can read about OrCAD Capture, go through brief descriptions of the available features, and access quick start guides and video walkthroughs. You can also access help content, product announcements, and industry news. The page provides contact information for your local channel partners or Cadence Customer Support.

17.4 Base Release

  • Simplified Project Creation and Simulation Flow. The 17.4-2019 release introduces the concept of universal projects, which allows you to create a project without having to select a project type. Further, with the new user interface, you can create a project along with the option to enable PSpice simulation. 
  • Streamlined Workspace. OrCAD Capture provides you with a large set of user-friendly tools and features to easily capture your schematic design. With the 17.4-2019 release, the workspace has been enhanced to ensure fast schematic design creation in an optimized manner. Many new improvements have been done in the Capture workspace to ensure greater ease of use and a satisfactory user experience. 
  • Application and Canvas (Schematic Page) Theme. In the 17.4-2019 release, Capture opens in a dark theme by default. A dark theme reduces power usage, improves visibility, and makes it easier for screens to be read. 
  • Well-Organized Toolbars. Toolbars have been reorganized according to function, and the icons in these toolbars are arranged based on their menus. You can toggle individual icons on or off in the toolbar. 
  • Workspace Customization. Panes are now displayed consistently across all OrCAD applications. All resources opened from a project are displayed as horizontal Tabbed Documents in the canvas area. By default, all panes displaying any kind of output are at the bottom of the application. If multiple panes are open in the output window, they are displayed as docked and tabbed panes. 
  • Enhanced Search Pane. The Find command is now available as a separate pane, called the Find pane. It allows you to specify a property value string and lets you select the object that you want to find. Capture then searches for all objects that match the specified string. 
  • Online DRC. The enhanced user interface of Design Rules Check introduces a new option—Online DRC. Set this to On if you want to check and list design rule violations dynamically as you create or update a schematic design. The Design Rules Check window enables you to set the rules to be run in Batch and/or Online mode. 
  • Design Sync. To efficiently and easily synchronize changes from schematic to layout, and from layout to schematic, a new user interface, Design Sync, has been introduced in 17.4-2019.Using the Design Sync window, you can view the differences between a schematic and the layout for a board, and synchronize the layout from schematic or schematic from layout. Designed with the capability for in-memory synchronization, you can use Design Sync to review the type of change, addition, modification, or removal of a design object without saving the design/layout. 
  • Accessing External Parts from Capture. Using the Place – Search Providers menu, you can search for and download millions of electronic components, symbols, footprints, manufacturer datasheets, and 3D STEP models from Cadence-supported content providers — SamacSys and Ultra Librarian (link is external). You can easily find the part you require and place it in your design. The part, its associated metadata, and any available ECAD models, are saved to your local library.

System Capture

QIR 3

  • Simplified Library Mode. Choose a library format when creating a design and library mode is displayed on the status bar. The library mode is locked when connected to a remote pulse server. 
  • Part Manager Enhancements. Updates to part version comparison and property placeholders are now displayed with the symbol graphic. 
  • New Controls for NetGroups and PortGroups. Hover over a netgroup to display all its members in alphabetical order including netgroups, buses, and scalar nets. Automatic creation and renaming netgroups and members. 
  • Session-wide Automatic Cross-probing. System capture can be set to always cross-probe and applies to all tabs across all applications (System Capture, Constraint Manager and PCB Editor). 
  • Layout File Support. Ability to view and create layout files is now included within System Capture. 
  • Usability Enhancements. System capture now supports grid units in mm and inches. Automatic identification of locale and location settings for menus, tool tips, errors messages and notes on the canvas. 
  • Symbol Editor Enhancements. Parts are now organized into categories, configure the default settings for symbols, and expandable/collapsible libraries. 
  • Reliability Analysis Improvements. Option to review device parameters before electrical stress analysis and waive device/audit check from the dashboard. Instead of full design simulation, subcircuit simulation is now available to save time and improve performance. New schematic audit rules added to analyze and improve your designs. 
  • Pulse Platform Integration. Improved integration including assigning permissions for block and pages and update notifications for linked schematic and layout. 
  • Build Complex Queries. Quickly identify parts in the unified search by building complex queries using search facets. 
  • CIS Manufacturing Information. Manufacturer part details are now support in the Unified search when defined in a linked CIS database table. 
  • Miscellaneous Improvements. Version support for special symbols, added source column in violation window, selection mode changes.

QIR 2

  • New Library Solution. Allegro System Capture now comes with a new native library format that also has complete in-tool support for creating libraries and parts. This means that not only can you create logical schematic designs in System Capture, you can now also create and edit libraries and parts 
  • OrCAD Capture Design Import. The direct library access for OrCAD Capture Libraries and CIS DB from System Capture has been enhanced in this release. You can now create System Capture designs that are based on OrCAD Capture designs as well as import OrCAD Capture designs as blocks into a System Capture design. 
  • Design Flow Features. Power and Ground Signals Connect to Vector Pins, Implicit and explicit Power Pins Connections now displayed in the property pin table, Support for splitting large pin-count design and the placement of the split parts is now available. 
  • Reliability Analysis. New enhancements including Assign or Change Device Categories, Custom Model Support, Additional Schematic Audit Checks, Temperature Sweep Support and Dashboard Enhancements for Device Log. 
  • Pulse Platform Integration. Pulse Platform Integration improvements including Team Design Enhancements, Design Project Creation From Templates, Addition of Electrical Parts to the Live BOM, and Local Parts Support in Unified Search. 
  • Usability Enhancements. Improvements to panning, support for 4K displays, links in session logs, navigation, easier selection of objects within shapes, common operations and more.

QIR 1

  • Continued Focus on User Interface Enhancements. Enhanced user experience as designs are created and managed across the PCB ecosystem. Changes to improve the ease of use and accommodate the newly added functionality to the properties window and preferences dialog box. 
  • Access to OrCAD Capture Libraries. Existing OrCAD Capture designers can directly launch System Capture and create a project that uses components from libraries configured for OrCAD Capture. OrCAD Capture Libraries and the CIS database is fully supported. 
  • New Wiring and Connectivity Engine. Changes that make routine wire drawing, moving, resizing, or pasting components or wires much smoother including guided bend points to avoid unintentional jumps and non-orthogonal wire support . 
  • Changes in Design Storage and Impact on Part Manager. The design storage architecture and part manager of System Capture has been enhanced to support the newly introduced concurrent team design feature. 
  • Design for Reliability. Using Design Integrity, you can run a reliability analysis of schematic designs opened in System Capture. Accounting for component variability and generating electrical stress analysis reports, Design Integrity determines circuit performance under a worst-case scenario thus shortening the design cycle. 
  • Pulse Platform Features. Enhancements to the Pulse Platform including Unified Search Supports Library Search, Sharing Designs Across Teams and Live BOM.

17.4 Base Release

  • User Interface Changes. Enhancements to the Project Viewer and Properties Window, Dockable windows, Optimized Toolbar, Special Symbol Preview and changes in Menus Shortcut Keys Behavior for improved usability. 
  • Enhancements for Object Selection and Replacement. Easily find and replace objects in the design with enhanced Selection Filter, and options to Replace Special Symbols and Replace Sheets Across Designs. 
  • Extended Design Reuse Options. Create New Project from DE-HDL and Import Voltage from Constraint Manager. 
  • Reporting Block Differences. A command-line utility is now available that compares logical connectivity between two designs, or two versions of the same design, and generates a list of netlist differences. 
  • Preserve Locally Edited Hierarchical Block Symbols. You can now edit the symbol for a block created by another user after instantiating it in your design hierarchy. 
  • Custom XNet Pin Pairs Definition. A new panel has been added to the Properties tab displaying XNet pin pairs
  • Improved Logging and Crash Handling. Event logging has been enhanced and all log files are stored in Pulse Data Mart. In the case of an unexpected tool exit, a zip file is created that contains diagnostic data. 
  • Pulse Platform Integration. System Capture now comes with embedded data management. Data is controlled internally when the Save command is used or Commit Points, which offers simple branching support, easy rollback and version preview without opening.

Pulse and EDM

QIR 3

  • New Feature for Designers in Enterprise Environments. Enhancements for web participants through project dashboard including access to unified search, project-specific BOMs, schematic version tree with viewable PDF, separated project BOM and Search tabs, and separate web browser tab support. Set component usage standards such as reliability, availability, EoL date, etc. 
  • Enhancements to Pulse Infrastructure. Designs can be automatically shared with users or groups on creation. Automatic logged into Pulse after any VPN connection interruptions due to network problems. 
  • Library Synchronization Service Enhancements. Options have been included for classification and property mapping between a PLM system and the ECAD component database system, library synchronization configuration management using the user interface, and using PTC Windchill with PingFederate. Enhancements in the Publish for Manufacturing Utility and Processing. Option to create or modify multiple templates, template assignment to users/groups, template import/export and the option to save template configurations in the Pulse platform. Link PLM Part Numbers with New Part Request to ensure that the central parts repository is in sync with PLM system.

QIR 2

  • Web-Based Access to Allegro System Capture Designs and Some Pulse Features. To simplify access to Pulse and its features for administrators and non-ECAD users who might not need access to authoring applications such as Allegro System Capture, PCB Editor, or APD+, this release provides you with a Web Participant. 
  • Enhancements to the Pulse Server Infrastructure. Cluster and Node Health Enhancements Distributed Debug Test Case Generation, Assignment of Multiple Roles to Users, Mixed Tier Support, and Unmanaged Library Support in the Pulse Server 
  • Adhoc Team Design for Allegro PCB and Packaging. Support for Allegro PCB Editor and APD+ designs within the Pulse platform. 
  • Auto-uprev of Pulse. When you open a Pulse-aware application, such as System Capture or PCB Editor, Pulse automatically updates its designs to the latest release. 
  • Enhancements in the Publish for Manufacturing Utility and Process. Windchill PTC Part Data Synchronization, BOM Data Sources in Publish for Manufacturing, Publish for Manufacturing Summary Report, and Publish for Manufacturing Completion Notification

QIR 1

  • Data Security with Authentication for Pulse PlatformThis release enables data security with authentication for users to work with the Pulse platform. To easily keep track of the number of users customers register with the Pulse platform, Pulse displays the user slots in the Pulse Manager page, which can be easily accessed via a browser. 
  • Enhancements in Pulse Cluster Manager User Interface. includes the introduction of an overview of the usage of all servers in the cluster, access to a greater number of services, and tooltips for each field. 
  • In-Design Workflows in Multi-User Environment. Centrally-managed, configurable task-oriented workflows, which are version controlled and allow role-based editing. 
  • Part Requests in Multi-User Environment. This release provides an option for designers to submit requests for new parts to librarians or for changes to existing parts. 
  • Enhancements in Publishing ECAD Data for Manufacturing. This release now supports custom variables, variant filtering and comparison, and variant specific attachments when publishing ECAD data to the file system.

17.4 Base Release

  • Pulse Platform. The desktop and server-based data platform of Allegro EDM is implemented in a microservice framework, referred to as Pulse. The framework provides services such as library management, the ability to search for parts, embedded data management, and enterprise PLM integration. 
  • Pulse Manager. A web-based administration console used to configure the Pulse platform. Easily accessed through a browser, Pulse Manager allows you to configure the Allegro EDM server and its clients, manage your logs, data, disk space quota, data backups, and various other tasks. 
  • Release to PLM. Enables users to easily publish design data, including the ECAD BOM and any manufacturing deliverables, to an enterprise’s PLM system or its manufacturing partners. 
  • Support for TLS 1.2 for Client-Server Communication. To continue to secure communication, privacy, and data integrity between the Allegro EDM server and its client servers, this release adds support for the industry-standard Transport Layer Security (TLS) 1.2 cryptographic protocol.

Allegro Design Entry HDL

QIR 2

  • XNets Status on Canvas. You can now show or hide a visual indication on the components with or without XNets.

Version 17.2

Products Covered: Allegro Layout Editors | Capture | Allegro Design Entry HDL

Allegro Layout Editors

QIR 7

  • DesignTrue DFM in OrCAD and Allegro PCB Editor. Design for Fabrication Rule Enhancements, Design for Assembly Rule Enhancements, Design for Testability Rule Enhancements including copper features, pacakge to package spacking, and design for test checks. 
  • DesignTrue DFM in Allegro PCB Editor Venture/Enterprise. Design for Fabrication Rule Enhancements, Design for Assembly Rule Enhancements, Design for Testability Rule Enhancements including micro via aspect ratio, package to package spacing, component lead checks, and design for test checks. 
  • Component Lead Editor in Allegro PCB Editor. Define lead type and physical details, position the lead in the symbol, view the lead contact area graphically, and enable DFM lead checks. 
  • DesignTrue DFM Ecosystem. Request fabrication rules directly from the supplier and receive those rules in the constraint technology file format. You can then directly import the rule files received into Constraint Manager. 
  • Allegro® PCB Symphony Team Design Option. Connect to a common database to perform collaborative design activities. Each team member sees the design updates in real time without generating or importing design partitions. Whether there is a formal project team or an ad hoc team, you can share the current design and invite other designers to join or assist. Symphony Server Manager provides remote management of Symphony server applications on a dedicated hardware server. 
  • Return Path DRC Enhancements. Now includes the ability to define table-based reference layer assignments at the net level. 
  • Sigrity Technology-Driven High-Speed Signal Analysis and Checking Enhancements. Two new Analysis Workflows are now available: Reflection Analysis and IR Drop Analysis. Updates to Licensing Use Model and general enhancements including net support in Return Path Analysis. 
  • Backdrill Enhancements. Ability to disable oversive antipads and keepouts. 
  • Component Group Move with DFA Feedback. DFA feedback in the form of a spacing circle for mulitple components. 
  • 3D Canvas Update. 2D Window Select, Reverse Cutting Plane and transparency control. 
  • Place Vision. Provides Guidance for Xnets rat filtering, timing driven placement and component association. 
  • OrCAD Professional Enhancements. Sigrity Technology Driven High-Speed Signal Analysis and Checking, Vision Manager, Timing Path support for Z-Axis Delay, Pin Delay Property for Extended Timing Path into Packages, Differential Pair Dynamic Phase Control, Backdrill, Net Group Enhancements, UI/UX Analytics, Design Previews, New Board Creator 
  • Miscellaneous Updates. Color Dialog Global Search now considers every class and subclass when searching. Modernized Command Pane is now a productized feature and no longer requires an environment variable

QIR 6

  • Enhancements in Design for Fabrication Rules. Exclude pin or outline to component checks. New Design for Assembly (DFA) Rules including outline, spacing, and pastemask rules. DesignTrue DFM in Allegro PCB Editor Venture Product updates including tented vias, void sliver checks, micro via stagger, outline to pin-pad exclusions, DFA (outline, spacing, pastemask, and fiducials) rules. 
  • Enhancements to Sigrity Technology Driven High-Speed Signal Analysis and Checking. Two New Analysis Workflows are available: crosstalk analysis and return path analysis. Return Path ERC now includes DRC to check for stitch via with radius from center of signal via. 
  • Dynamic Shape Quality and Performance Initiative. Dynamic shape voiding has been improved in this QIR. Abnormalities referred to as spikes or slits in shapes are addressed. This enhancement reduces or eliminates the need to add oversize clearance properties as a workaround. To improve shape voiding performance, a new Fast Mode has been released. 
  • Return Path DRC Enhancements. The Return Path DRC includes a check for stitching vias. 
  • Productivity Enhancements. Quickplace by Schematic Layout, Place Replicate Enhancements, Via Array Update, Route Clearance View, Enhancements in Copy and Paste Commands, Via Structure Update, Basic PDF Export, Show Measure Update, Mechanical Hole Checking, Zones with Placed Symbols 
  • Allegro® PCB Symphony Team Design Option. Symphony Team Design Enhancements including 3D Canvas support, Z-copy support, create bounding shape support and client cursor location and tracking. 
  • Productivity Toolbox Update. Testpoint to testpoint checking, Testpoint to component checks based on height depending spacings, Visualization of restriction areas, DRC marker generation, Constraints reuse through configuration files 
  • RF PCB Enhancement. A new library workflow has been introduced that uses unified RF library to support mixed MWO and ADS components in a layout design.

QIR 5

  • Return Path DRC Updates. The new Return Path DRC Vision option provides return path feedback based on the constraints system. Nets with a return path constraint assigned to them display trace segment color coding that indicates adherence to constraints. You can enable the Electrical Analysis modes for Return Path DRC in the online mode. The online mode keeps RC markers up to date without a Batch DRC update. 
  • DesignTrue DFM. DesignTrue DFM has been enhanced in the Venture license with the addition of backdrill. 
  • Allegro and OrCAD PCB Editor Canvas Enhancements. Improvements to the Start Page, Design Workflow Pane, Frequently-Used Icons, Customizable Design Canvas, Improved Graphic Response Time, and Modernized Command Pane. 
  • Find by Query Update. This command allows viewing of all the objects in the Find by Query dialog. You can query a design database for certain type of objects by filtering them based on associated properties. 
  • Route Vision (Segment Suppression in Pads). A new option to suppress segments that are entirely inside pads. This functionality reduces the report size by suppressing issues that are not present after the etching process. 
  • Timing Vision Update (Static Phase at Vias). Timing Vision has been updated to properly display phase information for the new static phase at via sites rule check. This functionality allows you to add phase rules to individual pin-via pairs. 
  • Productivity Enhancements. Including DFA Update, Assign Net to Via, Via Label Enhancement, Padstack Editor, File Locking, and Temp Group support in Application Modes 
  • Allegro PCB Symphony Team Design Option. Updates include hover over datatip for identifying lock owner, DRC Browser support, Read-only SKILL support, Integrated Design Analysis and Checking, Technology Dependent Footprints, Shape Editing, constraint edit mode, and symphony server. 
  • Common Allegro-Sigrity Material File File Format. A new file format that supports all material information is now available as an option for use in Allegro® and Sigrity™ environments. 
  • Miscellaneous Enhancements. Other enhancements include associated Components Support for Bypass Capacitors and Uvia/BBVia Spacing Support for Via Patterns 
  • IC Packaging-Specific Updates and Behavior Changes. RFPCB option is integrated into SiP Layout.

QIR 4

  • In-Design DFx. In-Design DFx Environment consists of bare-board fabrication checks that are defined as constraint sets in Constraint Manager. Constraint Manager contains a new Manufacturing worksheet. Allegro Venture PCB Designer and In-Design DFx Checks are expanded to address additional DFF checks and analysis that compliment the technology-based features.