Allegro Version History

The FIDES standard is now supported for real-time analysis to give better reliability results.

System Capture now supports locale language settings for Chinese and Japanese.

In addition to defining constraints at the block level, now you can define constraints on nets or pin pairs at the page level.

Filters are introduced for version metadata, layouts associated with schematics, tags, and comments. This is helpful when comparing versions or when rolling back to earlier versions. You can also edit tags assigned to previously committed versions of a design.

Project View and design view have been added to the open projects dialog box to search, filter and sort data.

New Tcl commands are added to enhance design data management in System Capture.

The thermal map generated for the board is now available as a tab within System Capture. Any analysis can be run in the thermal map tab. New icons have been added to the Thermal Floorplan results dashboard to support this integration.

RF blocks can now be imported into an existing System Capture design without affecting the design’s grid. The RF design gets imported as a read-only block if the grid settings do not match. A technology file can be directly exported from Allegro PCB Editor for CUL translation. The Cadence Unified Library Translator has many enhancements to support appending, deleting, or comparing translated libraries.

Components on the canvas can be directly added to a function. Changed parts in variants appear in a different color and alternate parts appear in italics. When rows or cells are selected, the count of the selected rows is available.

When designers want the library properties to remain in sync with the libraries or preserve overrides in the design, Part Manager flags user properties and you can replace these edited properties with the values in the library.

Expand or collapse Live BOM panels to view the graphical charts or data in more detail. Filters have been introduced to find the required information based on the specified criteria. To view part related errors and warnings, you can now click the parts in the table. Hover over the charts to see relevant parts based on their count and percentage.

Power symbols can now be replaced based on property.

Multiple pages can now be deleted in one go in the Project Explorer.

User-defined properties are now supported on the page border of the canvas. You can add, modify or delete them.

This directive controls which injected properties are to be excluded while checking for mismatched values.

Enhancements include permission-based design search results, four new sections to access required details (Project, Design, Layout, and Other), preview the schematic, view project details on the web, open linked layout versions of designs and blocks, visual indicators in search results help to identify recommended designs.

PFM is now supported in Allegro X Advanced Package Designer (APD). Administrators can specify a package as a layout source for .sip or .mcm files committed to Pusle. This enables layout engineers working in a pulse-enabled APD environment to publish ECAD data to the configured PLM system.

Publish for manufacturing provides options to extract and publish a set of metadata from Pulse to 3DEXPERIENCE to capture metadata about IC package designs in 3DEXPERIENCE for users who do not have access to the Cadence Allegro X Advanced Package Designer (APD) Application.

Support has now been added to deliver multiple files with a single utility.

A Filters option has been added to support version metadata, layouts associated with schematics, tags and comments. This allows you to compare versions or rollback to an earlier version.

Two default tags, Ready for Schematic and Ready for Layout, are available in an out-of-the-box Cadence installation when committing a design to Pulse.

Pulse administrators can customize the Live BOM summary pane by adding or removing widgets for a tailored view of the BOM summary. Changes can be published for all users connected to the server.

The previous Mandatory Utilities section is now revamped and renamed as Utility Selection Rules. In these settings, administrators can define which utilities must be run when publishing to a PLM System and define the default utilities for data publishing to a PLM system.

Enhancements to the 3DEXPERIENCE connector include a product number search enabling you to search by string, storing PLM revisions in the pulse project, assigning number filtering, and automatically filtering board numbers based on PLM structure to ensure that the assembly-board relationship configured in the PLM system guides you towards the proper board selection in PFM.

Live BOM updates include the following:

• • • Expand or collapse live BOM panels to view charts or data in more detail.
    • Filter the required information based on specified criteria and add filters directly from the table using icons on hover or clicking charts.
    • View part related errors and warnings by clicking directly in the parts table
    • Hover on charts to see relevant parts based on their count and percentage

The Unified search interface has been updated to include permission-based design search results. The User interface has been improved to include four new sections: Project, Design, Layout and other as well as including the ability to preview the schematic, view project details on the web, and open linked layout version controls for the design and blocks. Design rules can now be configured to include visual indicators in the search results to help users identify and select recommended designs.

DFA alignment can be used for group placement by selecting multiple components. Set the DFA_PAUSE_LEVEL to 4 in the User Preferences Editor.

When using the legacy DFA table you will receive an option to move to the new DesignTrue DFA table.

A new check has been added to check the pastemask against a component body (PLACE_BOUND or DFA_BOUND).

Configure your layout editor environment in a local language by setting Use local language under UI- Language & Fonts in User Preferences.

Switch the basic component overlap and height checks on the 2D canvas to utilize the DFA Bound shapes instead of the traditional place bound shapes.

The following enhancements have been made to the 3DX canvas:

• • • Cut the 3D view of the PCB in any combination of the X, Y, and Z axes to get the exact view required.
    • Control the color of all manufacturing materials to produce photo realistic 3D images
    • Increase detail and control of visibility and transparency for detailed 3D views
    • Customization of the 3DX canvas with visibility and preferences
    • Control the display of 3D spacing violations to see space overlaps and space needed.
    • Measure the 3D air gap

Copy and paste pad geometries within the same tab or between the design and mask layer tabs to save time during padstack creation.

Configure the plot setup for generic operating system-related page setup in the preview window along with other advanced options.

Customize the timing meter colors. Colors are no longer limited to the defaults of Red (Error), Yellow (Warning) and Green (Pass) conditions.

High-Speed interfaces require special treatment to avoid signal integrity issues under components and component pins by generating openings in adjacent planes while preventing routing from running through these openings in the planes. Now you can automatically generate adjacent keepouts by tagging certain components, pins and nets that require this treatment.

Adjacent keepout definitions can be managed on the schematic or layout and can be transferred back and forth using the Front to Back Flow.

Manage and edit the properties in the layout editor using Properties or inside the Constraint Manager.

Manage net properties in the properties section of Constraint Manager. Use the electrical properties worksheet to enable nets or groups of nets that should have dynamic adjacent keepouts generated.

Automatically generated keepouts are associated with component/pin and move/mirror along with the component, including during zone and embedded placement.

A new Query Based Rules workbook is available in the same net spacing domain and drives spacing rules between vias padstacks in the design. This allows a high level of flexibility in developing specific Same Net Via to Via rules based on groups of Vias, trace connected or not trace connected (stitch vias).

Sometimes you need to reduce trace width when routing through BGA pin fields, which results in a higher impedance causing signal integrity issues. Enhancing traces with small trapezoidal copper shapes (routing tabs) lowers impedance to avoid these impedance discontinuities. Tabbed routing has been enhanced to improve net selection and analysis. The Xnet dialog box has advanced filtering and hierarchical group selection to ensure all nets are selected for analysis. Improved analysis dialog box includes net groups and differential pair membership for each row allowing a more focused review by sorting results. Additional options are available to verify tab counts between net group members or between the nets within a differential pair.

Ensure the internal markup and comments are not exposed to external resources when you send the designs out to third-party vendors. Quickly remove comments and markup from the database and archive them to a local file.

Generate a thermal floorplan to estimate the life of the PCB design and improve placement of components early in the design cycle.

Launch Topology Workbench directly from the System Capture canvas to analyze the signal integrity of high-speed nets at the schematic, floorplan, and layout stages.

Perform MTBF analysis on a design to estimate the performance and safety of electrical, mechanical, and electro-mechanical parts for Allegro X Designer and above.

Enable the verification of all the components in a design in the early stages. Set up a power distribution network on the schematic to estimate the DC power consumption by components in the PCB design for Allegro X Designer and above.

In addition to adding parts from external content providers directly into a design, Unified search now supports adding parts to libraries from SamacSys or Ultra Librarian.

Create a new template library, create categories and subcategories in libraries to improve component searching, edit multiple parts in a spreadsheet and enhanced part validation improves the library authoring experience.

Integration to AWR Microwave Office and Allegro PCB Design applications provide a way to create complex PCBs with RF design. Enhancements to this integration include a single impot from AWR Microwave Office into System Capture and more.

May enhancements have been added to efficiently complete variant designs including creating function groups, defining alternate parts, defining variants, and the ability to switch to variant views.

System Capture now offers long-term archiving ability with the PDF/A format in addition to the PDF and SmartPDF formats.

Allegro X EDM library parts can be updated with changes in the Windchill part data and vice versa.

Enhancements to the Pulse Web Dashboard are available to single-user and multi-user environments of System Capture. Enhancements include additional filters, save column visibility, project-specific URL for bookmarking, and more.

Easily compare two versions of a design to determine the correct path forward as a team. Compare the latest revision or the previously committed version of the design.

Users in a multi-user environment can disconnect from the Allegro Pulse server and work in the offline mode, ensuring uninterrupted work using parts in the design cache.

Cadence Doc Assistant presents help content as individual easy-to-read topics and has improved the speed and relevance of search capabilities.

Define secondary drill definitions on either the primary or secondary side.

Expanded the capability of microvia drill support beyond circle and square-plated holes to include microvia slot. This allows rectangular or oval-plated slots while following standard microvia constraints in the design.

Drilled hole fields for circle and square holes as well as round slot fields for rectangle and oval shot holes have been added for accurate unit-controlled values of the drill hole size before plating and tolerances.

Pitch values for rows and columns can now be defined to calculate the spacing automatically for a multi-drill.

When dynamic shapes need to remain constant to protect critically circuitry and maintain design intent, suspend or freeze dynamic voiding instead of converting to static shapes. Once frozen, new objects entering a shape will not void and will generate a DRC error.

Components placed in a zone with some of the pins protruding into another zone can cause buried or floating pins. Easily check to verify that all pin pads of a component exist on the same placement layer.

Designate stackup differences in particular areas of your rigid-flex designs by defining one zone inside another for scenarios where one shape needs to be surrounded by another.

Zone modifications can now be performed without activating Shape Edit Application Mode.

Define the fill-in material for multi-layer PCBs to account for the different dielectric constants that affect the electrical characteristics of conductors running across the dielectric​.

Facilitate a collaborative design review environment with the ability to markup and comment design feedback directly in the PCB canvas. Markups are stored in the design database, streamlining the design review process.

Automatic mapping and fine-tuning of the x, y, and z placement provides efficient methods for mapping 3D models to the footprint directly in the library.

Export the complete 3D representation of the entire design or individual objects as STEP, IGES, ACIS or a PDF.

Define dimension parameters to apply a line width globally for all dimensions.

Define the net during Z-copy to copy etch shapes to other layers. Incorporate a subclass wildcard to copy the shape to multiple layers.

A new delete option will remove routing from the previous module for components that are part of another module.

Reuse device files and component definitions that are currently in the design when loading an updated netlist.

New net short properties report is available to easily find all the objects in the design with the Net short property to verify the nets being shorted.

New high-voltage constraint checks to verify creepage and clearance rules. Design Rule check system recognizes non-plated slots between two high-voltage objects and recalculates creepage and clearance. Creepage and clearance vision provides graphical feedback with color-coding directly on the canvas for efficient analysis.

Quickly generate power planes for a section of the design of the entire design based on pin placement, boundary, or design outline. Review power plane escape and adjust placement or constraints to improve power connections.

A new routing tab utilizing complex shapes that follow serpentine pattern contouring to pins and vias allows you to maximize tab size and reduce impedance when routing through CPU pin-fields.

Performance and response time has been improved for opening and saving designs, wiring, and canvas selection.

Configure System Capture to show the winning or base net on the canvas when multiple nets are aliased.

Specify a prefix or suffix for blocks in hierarchical designs. This suffix or prefix is automatically applied to the physical net names for nets and buses.

Blocks and pages can be excluded from printing.

Page border symbols and properties on page borders are now brought in as properties when designs are migrated from DE-HDL.

To avoid accidental editing of designs, especially in a team design environment, lock a design block or page to enable a read-only status and watermark.

Find and replace feature is now enhanced to replace special symbols such as power, ground, or ports.

Define the default behavior for wire name assignment and display settings when wires are connected to a power source or copying circuitry.

For multi-section instances or split instances, all sections are processed in a single transaction, enabling reference designator preservation.

In hierarchical blogs where the number of bits were reduced, automatically purge the deleted bus bits.

Select a group of components on the schematic canvas and assign pin numbers based on data from the part definition when working with single-pin multi-selection components.

Specify a part code and add a preferred part regardless of the availability of parts in project libraries. Add this preferred part for any variant using a placeholder part number or browse through available parts to choose one.

Do Not Install (DNI) components in the base design can be indicated with a cross over the component.

Quickly identify the nets that are perfect matches or partial matches in the Port/Pin Assignment dialog box with color coding.

Print system -level designs in all print formats including PDF and Smart PDF.

Link the .MCM files from ADP Plus and Allegro System Capture schematic to ensure your project stays in sync.

Edit Allegro DE-HDL libraries directly within System Capture and launch OrCAD Libraries to create or edit OLB schematic libraries.

Improve design creation and quality with additional rules including connectivity checks for MISO and MOSI pins, ref des visibility checks, fiducial checks, test pad checks, and more.

Updated Tcl commands and new directives to improve customization.

Define a single source for a layout design within pulse to generate all outputs to Publish for Manufacturing.

A non-analysis version of Topology Workbench for constraint capture is now included.

When reusing structures multiple times, easily update one instance and push the changes to all instances.

Easily convert objects and create or replace an object with a padstack directly on the canvas.

Easily make changes to a dimension without having to delete and regenerate it.

Easily locate stacked vias and flag them with DRC markers in restricted areas.

Enhancements include better performance on designs with a large number of DRCs, faster update to smooth, better move performance, better performance for shape parameter per layer override, capping of command window messages, and faster DRC checking on designs with negative layers.

GPU support now includes modern discrete or integrated GPUs from Intel and AMD. Enhancements to NVIDIA GPUs include performance gain in panning and zooming and augmented quality of display.

Easily specify a scaling factor to normalize forms that are partially cut off due to display scaling in devices with 4k or higher resolution.

Faster structure creation for parameterized high-speed structures by leveraging information from other areas and extracting information from selected differential pair transitions.

Replace via with structure has been updated to accept structures that do not contain pad entry or exit traces maintaining current routing and delay matching.

Choose a library format when creating a design and library mode is displayed on the status bar. The library mode is locked when connected to a remote pulse server.

Updates to part version comparison and property placeholders are now displayed with the symbol graphic.

Hover over a netgroup to display all its members in alphabetical order including netgroups, buses, and scalar nets. Automatic creation and renaming netgroups and members.

System capture can be set to always cross-probe and applies to all tabs across all applications (System Capture, Constraint Manager and PCB Editor).

Ability to view and create layout files is now included within System Capture.

System Capture now supports grid units in mm and inches. Automatic identification of locale and location settings for menus, tool tips, errors messages and notes on the canvas.

Parts are now organized into categories, configure the default settings for symbols, and expandable/collapsible libraries.

Option to review device parameters before electrical stress analysis and waive device/audit check from the dashboard. Instead of full design simulation, subcircuit simulation is now available to save time and improve performance. New schematic audit rules added to analyze and improve your designs.

Improved integration including assigning permissions for block and pages and update notifications for linked schematic and layout.

Quickly identify parts in the unified search by building complex queries using search facets.

Manufacturer part details are now support in the Unified search when defined in a linked CIS database table.

Version support for special symbols, added source column in violation window, selection mode changes.