Cadence OrCAD is a driving force in the PCB design industry. In order to help designers keep up with the constant pace of change Cadence has been accelerating the pace of innovation delivering a stream of updates and product enhancements to users. The release history below provides insight into industry-first capabilities made available to customers such as real-time design, DesignTrue DFM, constraint manager, in-design analysis, and more.
Real-Time Interactive 3D Design
See how interactive 3D in OrCAD helps you design in real time with greater accuracy.
Real-Time Route Analysis
Real-time interactive checks help you easily find and fix common route quality issues that manufacturing DRC signoff checks miss.
Real-Time Placement Analysis
Visual indicators of length constraints help you meet delay propagation and total etch length goals when placing components.
Real-Time Impedance Analysis
Easily and quickly identify impedance discontinuity issues visually, without simulation models or extensive signal integrity expertise.
Real-Time Coupling Analysis
Easily and quickly identify coupling issues without always having to rely on the SI expert.
Real-Time Manufacturing Checks
Break out of the find, fix, reiterate cycle with over 200 configurable real-time design for manufacturing checks and get your design right the first time.
Version Notes:
Products Covered: OrCAD X Capture CIS | OrCAD X PCB Editor| OrCAD X Presto | PSpice
OrCAD X Release. Innovative design platform focusing on providing a cohesive and comprehensive solution for all design requirements.
Products Covered: OrCAD Capture | OrCAD PCB Editor| PSpice
Products Covered: OrCAD Capture | OrCAD PCB Editor | PSpice
GPU Acceleration Rendering. Leverage GPU in Allegro Layout Editors to improve response time during panning and zooming, toggling layers, and render quality.
DRC Browser Updates. Navigation improvements for the DRC Browser and the ability to waive DRC by group select.
Fillet DRC Control. New analysis mode option to enable line based checks for fillets.
Shape Performance and Quality Updates. Improved shape performance for copper pours and editing smooth shapes. Fast mode replaces rough mode and drastically improves the performance during active etch editing including slide, add connect, move, and more. Improved performance in shape voiding quality including crosshatch shape fill improvement, fillet void quality improvement, and trim void improvement.
3D Canvas Updates. Isometric view has been added for the bottom side of the board. Other updates include realistic plating thickness, increased model realism, and secondary model support.
Reuse Module Enhancement. Dynamic shapes are automatically converted to static shapes to ensure consistent voiding. Modules applied to the design remain locked to avoid accidental modification. Addition of copper planes, constraint regions and text notes within the module file. Quickly swap a placed reuse module with a different variant in one or multiple locations.
Scribble Enhancements. Multi-pin scribble support when routing allows you to digitize a path through a pin field to make connections. Recognizes the same net pins and snaps to center while routing.
Viewer Integration. Launch PCB Editor viewer from the project hierarchy.
3D Canvas enhancements. 3D mapper now a part of 3D canvas, replacing Allegro (2D) menu. Simplified use model and GUI enhancements. Improved accuracy of collision detection and distance measurements. Additional support for mapping native CAD models (Parasolid, Siemens NX, CREO, SOLIDWORKS).
IPC2581 enhancements. Additional support for rigid flex (bend detail and stack-up profiles), Countersink/counterbore, square drill features, net shorts, and impedance specifications and nets.
IDX enhancements. Bend sequence ordering, Geometry use identification, primary pin identification, and time stamps.
PCB Panelization. Setup and manage your fabrication panels directly within PCB Editor (OrCAD Pro & Allegro Feature).
New Design Setup Workflow. You can now use the new Design Setup Workflow to prepare for analysis by setting up your design for the different checks. You can set up cross-section, DC nets, components, Xnets, and differential pairs. You can then save the design with the changes. As with all other work flows, you can access this workflow from the Analysis Workflows pane (Analyze – Workflow Manager).
3D Canvas Updates. A number of improvements and enhancements have been made to the 3D canvas including:
IPC 2581 Spec Properties. By defining a SPEC that is composed of the fabrication notes, the notes become part of the IPC-2581 data and are directly read by an IPC-2581 viewing tool, reducing the need to locate the correct drawing or document to read the notes. Another example would be to define assembly notes for a heat sink to be added to a part. The assembly note might instruct users to add a specific thermal epoxy first, then add the heatsink after the epoxy is applied.
Mask Defined Pin Annular Ring Check. A new Mask Defined Pad check has been added to the Design for Manufacturing Annular Ring checks and the DesignTrue DFM Wizard template file. There are two common types of padstack definitions when it comes to soldermask to pin pad size ratios. The first, metal-defined padstack (sometimes referred to as non-mask defined padstack), is where the solder mask opening is typically larger than the pin pad. The other is a mask-defined padstack, where the solder mask size is typically smaller than the pin pad. The mask-defined pad is often used for BGA components to contain the solder ball within the pin pad and prevent outflow of solder.
Hierarchical Route and Via Keepouts. You can now define keepout by layer type and location using the additional Route and Via Keepout subclasses that have been added to Symbol Editor. Following a model similar to Constraint Regions, use the OUTER_LAYERS, INNER_SIGNAL_LAYERS, and INNER_PLANE_LAYERS subclasses to create keepout shapes.
Contour Routing Update. The 17.4-2019 release now supports the previous Enhanced Contour behavior as the default contouring method. In addition to the previously supported functionality of latching/unlatching and shoving, this release focuses on ease of use and power by adding additional spacing controls and full constraint region support.
Copy/Paste Update. In previous versions of layout editors, copying of objects was performed by selecting objects and pasting them to one location at a time. While the use model was simple, the functionality was limited. The 17.4-2019 release aligns the copying functionality of the layout editors with other popular software applications by adding familiar behaviors. This new copy command combines the precision of single click or single location pasting with the power of window select or multi-location pasting. As with most applications, copied objects are buffered for pasting at a later time. You can paste the last copied object at any time simply by using the paste command.
Copy. The Copy command now adds the selected objects to a buffer and automatically starts the Paste command to enable the placing of objects on the canvas.
Paste. The Paste command supports all legacy “copy” options as well as new support for shape net retention. In addition to these options, pasting can be used in two different manners:
3DMechanical Symbol Transparency. Designers who wish to “peek” inside a PCB assembly encased with a mechanical cover can now do so. Now look through the mechanical cover into an assembly by setting the global transparency/opaqueness setting.
Unplated Holes in Footprints. Unplated holes in footprint (.dra) files can now be visualized when the footprint is brought into 3D Canvas. Previously, unplated holes were not represented.
STEP Models and Pastemask. In some system designs, such as complicated telephony devices, even the most minuscule space is critical. With the 17.4-2019 release, the position of 3D models can now be globally adjusted to take the thickness of solderpaste into account in the “z” direction. By default, the STEP model location in the “z” direction is the bottom of the model located directly on top of the copper pads.
Access to TI Libraries. Access additional Texas Instrument Libraries from OrCAD Capture including 5000 TI-PSpice Models across 100 unique model categories and as many as 4000 test circuits.
Improved Usability. Auto launch of PSpice on new project creation, updated menus, and updated PSpice search.
MATLAB 2020/2021 Support. MATLAB 2020/2021 support is now available for PSpice co-simulation flows.
Usability updates. Get notified for missing parts for your PSpice models as you place them with Online DRC. Navigate warnings and errors with cross-probe between DRC and schematic. PSpice parts are loaded automatically when a new PSpice project is created. Improved capture integration with the ability to view PSpice models within Capture.
New modelling applications. Easy-to-use DIODE and MOSFET model parameters from device datasheet, specifically targeted for power applications.
Products Covered: OrCAD Capture | OrCAD PCB Editor| PSpice
Enhancements in Part Editor. With QIR 7, you will see the following enhancements in part editor:
Simplified Interface for Associating a PSpice Model. You can now accomplish the following tasks to associate a PSpice model using a simplified user interface:
Performance Improvement. Performance has been improved for various design specific cases, such as designs with large number of netgroups.
Design View in HTML. This new feature allows you to export a complete schematic design as a single HTML file, and view the design in the specified internet browser (Google Chrome recommended).
Saving Design Differences to HTML or Excel. OrCAD® Capture Design Differences Viewer now supports the ability to save the design differences into HTML files (.html) or Excel files (.xls).
Passport Protection to a Design in Capture. You can now add a password to a design, remove an existing password applied to a design, or modify an existing password applied to a design.
Configuring Properties. You can configure the Find window properties and Browse Parts window properties using the Configure Properties window.
New Utilities. New utilities have been added in OrCAD Capture to automate some of the manual tasks, including: Communication Server, Replace Path in Design Cache, Show All Open Libraries and Design, Customize Page, Check/Correct Corrupt Library, and Find and Replace Text.
Display Checkbox in Add New Property Dialog. Enable display of user-defined properties so that you can set display properties while creating a new user-defined property.
Updated Property Editor Filter in the Properties Editor Window. Updated and flow-wise property spreadsheet filters are now available, so you don’t need to search for commonly used properties for a flow.
Global DRC Settings for Global Environments. A new option, Use Global DRC Settings, has been added in the DRC tab of the Extended Preferences Setup window. By enabling this option, you can use the same DRC settings globally for various different designs to enable standardization of a DRC setting across projects, sites, and teams
Design Difference Viewer. New feature to perform logical and graphical comparisons between two designs, two schematic folders or two schematic pages and view the difference report in the form of a portable HTML format. (Watch Demo Video)
Open Demo Design. The new Open Demo Design browser gives access to more than 150 demo designs made available from different locations, collated together to help users better understand Capture, Capture CIS and Capture _ PSpice Flow.
Export – Import XML. OrCAD Capture provides you the capability to convert Capture designs to XML format and vise-versa based on the requirement.
ISCF Export. Introducing direct ISCF (Intel Schematic Connectivity Format) feature for automating Intel-based design reviews to export hierarchical schematic designs in an Intel-approved format helping you optimize the design review process.
PDF Export. The new PDF export functionality lets you export Capture design as PDF file and provides intelligent design information.
Extended Preferences setup. The extended Preferences Setup window allows you to modify additional application settings in OrCAD Capture like Command Shell, design and libraries, design rule check, CIS, NetGroup, NetList, and Schematic.
Advanced Annotation. The new advanced annotation feature lets you annotate multiple schematic pages at a time giving them complete control over their component annotation process in the design cycle. (Watch Demo Video)
Design for Fabrication Rule Enhancements. In the Design for Fabrication constraints, a new category Copper Features has been added in this release. This category applies rule to cover minimum line width, antenna, and acid traps.
Design for Assembly Rule Enhancements. A new category PkgToPkg Spacing has been added in the Design for Assembly constraints. You can now maintain the DFA table within Constraint Manager and assign different DFA rules based on stack up technology, specifically within rigid-flex designs. All existing functionalities are still maintained from previous versions.
Design for Testability Rule Enhancements. A new Design for Test constraints have been added in the Manufacturing category in the QIR 7 release. These group of checks are related to issues in the final testing of the PCB assembly.
DesignTrue DFM Ecosystem. To make designs ready for fabrication, the information about various manufacturing constraints and rules and the supported values are obtained from PCB fabricators in the form of spreadsheets. The spreadsheet is then transferred into Constraint Manager by a PCB designer. This process is error-prone and time consuming. The easiest way to obtain the rules would be in the form of direct import of fabricator rules into the Constraint Manager using technology files recognized by Constraint Manager.
DesignTrue DFM Web-Based Rules Request. The DesignTrue DFM Partner Program was developed to facilitate the request for fabrication rules directly from the supplier and receive those rules in the constraint technology file format. You can then directly import the rule files received into Constraint Manager.
To request rules, open the request login site from a Web browser at https:\\pcb.cadence.com\dfm_customer.
3D Canvas Update. The recently productized 3D Canvas continues its growth and maturity with the QIR7 release. With additional features still under development, this release covers incremental updates that will enhance the user experience.
Selecting a specific area of a design to visualize in 3D is now easier with “window select” on the 2D workspace
The popular Cutting Plane feature has been supplemented with a “reverse cutting plane” option
The original Perspective View has been paired with an additional Orthographic View choice
The 3D Canvas now recognizes STEP model colors assigned in the STEP Package Mapper
Color Theme layers now have transparency control sliders and objects falling within holes
Cutouts and outside the board outline are now eliminated from view
Place Vision. Place Vision, available in PCB Editor, is a graphical environment designed to increase productivity and efficiency with various component placement strategies. While the concept is similar to Timing Vision, Place Vision offers guidance with respect to:
Xnet rat filtering
Timing driven Placement
Component Association
Sigrity Technology Driven High-Speed Signal Analysis and Checking. OrCAD® Integrated Analysis and Checking is a new, unique environment blending the best of OrCAD® and Sigrity™ technologies that provides analysis and checking capability entirely within the PCB Editor framework. For rule checking, DRC and ERC capabilities continue to depend on Constraint Manager as the single cockpit. This release introduces two new workflow analysis capabilities for impedance and coupling. The workflows provide guided access to Sigrity analysis with results returned as dockable tables and plots, or as new Vision overlays.
Timing Path support for Z-Axis Delay. The Z dimension of Vias and Through Hole Pins can now be included in timing path DRC calculations.
Pin Delay Property for Extended Timing Path into Packages. System level constraints typically require the creation of a Design Link and possession of mating boards or package databases in order to create a multi-board constraint solution. A timing path from the die of one chip to the die of another requires the MCM file from Allegro Package Designer (APD) or SiP Layout to create the extended timing path. Obtaining these databases from Chip vendors is not always possible and the alternative for many was to create formulas in applications like Excel. The Pin Delay property allows external delay values like package length to be entered into the OrCAD PCB Editor and assigned to a component from a CSV file, assigned as properties/values to pin instances, or entered in the PIN Delay column of the Propagation Delay or Differential Pair worksheets in Constraint Manager.
Differential Pair Dynamic Phase Control. Differential Pair technology has evolved where more stringent checking is required in the area of phase control. This is evident with higher data rates associated with parallel buses. In the simplest of terms, Differential Pair technology is sending opposite and equal signals down a pair of traces. Keeping these opposite signals in phase is essential in assuring that they function as intended. As the current “Static Phase” is limited to a one time check across the entire Driver-Receiver path, the “Dynamic Phase” check performs phase checks at bend point intervals across the differential pair. The check is designed to meet the guidelines suggesting the path lengths of the true and complement signals within the differential pair must differ by no more than “x mils” along the entire path of the net. If at any point on the net, the skew between true and complement exceeds “x mils”, this mismatch needs to be compensated within “y mils”. Representative values for x and y might be x = 20 and y = 600.
Backdrill. The Backdrill application, originally introduced in the Allegro PCB Editor, has undergone some significant enhancements and now introduced to OrCAD Professional. Backdrill data is now stored in the library padstacks and utilized at the design level during the analysis and backdrill generation process. Padstacks which do not have predefined backdrill information can be automatically updated at the design level by the entering the backdrill criteria prior to running backdrill. Design layers which are backdrilled will have Route Keepout Shapes generated to ensure design integrity is maintained with separate padstack definition controls for the backdrill start layer, internal layer and negative layer anti-pad geometries without the need of custom padstacks or scripts. All backdrill data is available on the individual Pin/Via objects displayed on the canvas or by simply querying the object using Show Element, and generating the Backdrill Legends and detailed Backdrill Report. In addition, the setup time for backdrill can now be improved as a result of algorithms designed to create intelligent layer pairs.
Net Group Enhancements. The Net Group constraint object introduced in release 16.6 to replace the Bus constraint object has been enhanced in OrCAD Professional to support Nesting conditions. This may be useful in defining High Speed Interfaces.
Design Previews. QIR 7 introduces design previews for a faster way of identifying and opening designs. Located on both the start page as well as the “open” dialog, users are now presented with a visual representation of their board files. Previews are generated and linked to the database with each save to ensure that they are always up to date.
New Board Creator. When starting a new board file, you are presented with a dialog allowing for quick and easy database setup. Using the same parameters as found in the Design Parameters dialog, you can adjust the database units, sheet size, accuracy, extents, and origin location for designs. As the you update or change the parameters, the dynamic preview located on the right side of the form updates to reflect the selections. The origin is represented by the location of the red dot.
New Design for Assembly (DFA) Rules. Newly added Design for Assembly (DFA) constraints are located under the Manufacturing category in Constraint Manager.
DFA Outline Rules. Outline checks for DFA provide rules for checking minimum spacing between component bodies to the DESIGN_OUTLINE and component bodies to CUTOUT subclasses. For every component, DFA_BOUND takes first precedence followed by PACKAGE_BOUND.
Minimum spacing for pastemask to DESIGN_OUTLINE and CUTOUT subclass rules are also part of this category.
DFA Spacing Rules. Minimum DFA spacing rules for various mechanical hole types to component bodies, as well as component pins to other component bodies, are defined in Constraint Manager. Other spacing checks include pastemask to pastemask and pastemask to via minimum spacing.
DFA Pastemask Rules. Pastemask checks detect the annular ring of the pastemask to SMD copper pin pad, missing pastemask on any SMD pin pad, and pastemask to other mask openings, such as soldermask and coverlay.
STEP Package Mapping. The ability to remove the mapping of all STEP models to all symbols in a layout has been added to the Device/Package STEP Mapping dialog box. Click Purge button located in the lower center of the dialog box. A confirmation message displays.
STEP Export Options. An option to use the basic symbol geometry and ignore mapped STEP models for of a layout drawing to a STEP file has been added. Enabling the Ignore STEP model definitions option in the STEP Export dialog ignores the STEP models assigned to the package symbols during the export process. The place_bound height associated with those symbols are exported instead. Enclosure and assembly models are still exported as 3D STEP data.
Refresh Symbol Enhancement. You can now refresh symbols to the latest STEP models. A new option Update STEP mapping data only has been added in the Update Modules and Symbols dialog box.
Dynamic Shape Quality and Performance Initiative. Dynamic shape voiding has been improved in this QIR. Abnormalities referred to as “spikes” or “slits” in shapes are addressed. This enhancement reduces or eliminates the need to add oversize clearance properties as a workaround.
Place Replicate Enhancements. The MDD files can now be reused and replicated on boards with differing stackups. When a module stackup does not match the target board stackup, the layer mapping window appears. This window allows quick drag and drop operations to adjust and map the module stackup to the target board. Color coding helps to easily identify plane layers and signal layers. All via types are supported including through, micro, blind, and buried. Currently, all module layers must be mapped and reordering of module layers is not supported.
Route Clearance View. A new option Clearance View is added in the Options pane of the add connect command. When enabled, generates polygon around
