This workshop will teach you how to analyze DDR5 performance during the PCB layout to find and fix errors before production.
Designing with DDR5 introduces new complexities to PCB layout and simulation due to the increased speeds, lower power, and new operational functionality present in these devices. JEDEC releases standards and specifications to help guarantee DDR5 operation; however, when adequate performance metrics are not achieved, identifying and resolving issues to improve signal performance can be very difficult, especially after PCB production.
Throughout this workshop, Sigrity Advanced SI will be used to simulate and analyze DDR5 performance. Don’t have Sigrity Advanced SI? Request an evaluation here to follow along.
This workshop is based off of Stephen Newberry’s webinar, DDR5 Post-Layout Verification: Find and Fix Causes of Failure. This webinar provides an example of a DDR design reporting failures even though a pre-layout analysis was performed to determine the optimal constraints and the layout looks adequate during visual inspection. With short timelines and time-to-market goals, this webinar demonstrates how to chase down the root cause of the failure in time to ship the board. It gives hardware engineers, PCB designers, or signal integrity engineers the tools they need to avoid these pitfalls up front as well as the skills to troubleshoot the problems when they do arise.
This workshop will expand on the DDR5 Post-Layout Verification webinar, teaching you how to analyze your PCB design to ensure DDR5 performance in accordance to JEDEC standards, what performance metrics should be analyzed, and how to identify and resolve errors during the PCB layout to improve DDR5 performance.
