Cadence Allegro PCB Design Platform

“ With Allegro TimingVision, everything is right there in front of you—this simple fact allows the routing process to be sped up dramatically, from the manual routing efforts we have seen that can take up to four weeks, down to four days.”

Bill Munroe, Principal PCB Designer  | Cavium

"Instead of starting with FPGA code and forcing pin assignments onto the schematic engineer and FPGA designer, we can plan pin assignments first using Allegro FPGA System Planner and then move to RTL code true FPGA and PCB co-design. With pin coding established at an abstract level, we can save one or two months of work. Considering that our FPGA-based design has around 800 pins, the impact is substantial."

Daniel Charlet, Design Engineer | IN2P3

"It was remarkable. To be able to consolidate backdrilling depth with ease on a big board like that was a dream. Now when we release a board to manufacturing, our confidence is pretty high...One revision was totally unthinkable before.”

Boris Nevelev, Senior Hardware Design Engineer  | Imagine Communications

With auto-routing, we certainly got through routing quicker, and spent more time upfront entering design constraints and doing the process of correct-by-construction...Allegro PCB Router helped us shave off a few weeks of overall cycle time. This is critical in getting our boards to the lab, finding bugs, and shipping our board —all of which we can now do earlier.

Greg Rousch Engineering Manager | Polycom

“Cadence has done a lot of good engineering work to come up with a methodology for driving down the micro vias through the layers to get the correct via structure, spacing for the vias themselves, through-hole vias, and to other metal shapes and traces in a design...We are shaving up to 25% off our PCB layout design cycle time for complex high-speed designs that use HDI technology."

Greg Bodi, Senior Manager, System Design  |  NVIDIA

Auto-routing took away the worries. Before we release a design, we can run reports in Allegro PCB Router with exact checks against our design constraints, and flag any parameters that haven’t been met. As a manager, that made me feel way better— that we’re not missing anything.

Greg Rousch, Engineering Manager | Polycom

“Before, we had to run the full board design chain before we could see if there would be enough room for all of our components. Through a manual process, we would have had to spend a lot of time optimizing connections of this 1,920-pin FPGA and the layout of quite sensitive 10 Gb/s connections. With Allegro FPGA System Planner, we can quickly ensure that pin placement and routing are correct. We can also change FPGAs and other components very quickly in our design, without having to do a time-consuming manual schematic update effort.”

Daniel Charlet, Design Engineer | IN2P3