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Whitepaper

Serial Link Engineering: A Novel Jitter/Noise Metric to Qualify Channel Components

This whitepaper will discuss a novel eye-area based normalized jitter and noise metric for serial link analysis.
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Whitepaper

Rocket EMS Shares First Pass Design Success Tips

Learn a systematic approach to change the often LOSE-LOSE relationship between a contract manufacturer (CM) and startup to a WIN-WIN.
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Whitepaper

Rigid Flex: DFM and Design Rule Considerations

This paper discusses some of the key challenges to address and also introduces a new PCB design approach that enhances productivity through in-design inter-layer checks required to ensure correct-by-construction design.
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Whitepaper

How to Define and Add Interposer to Your Die Stack

In this document, you will learn how to create an interposer library object and place an instance of that definition into your SiP substrate design.
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Whitepaper

How to Create a Symbol from SiP and Import into Virtuoso

This document will help designers use chips and connectivity from SiP Layout to create a symbol in Virtuoso, saving time.
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Whitepaper

How to Convert a UPD Package Substrate for Use with APD and SiP Layout

This document describes the procedure to import UPD spd2 format files in Cadence Allegro Package Designer (APD) or SiP Layout tools and creating your APD/SiP Layout libraries based on imported data.
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Whitepaper

Export DIE abstract (XDA) from Virtuoso for use with SiP Layout and OrbitIO

After going through this application note you will be able to export DIE data from IC (Virtuoso) to Cadence Chip packaging tool (SiP and OrbitIO).
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Whitepaper

ECO Process for Cadence SiP

This application note will go through the flow and process needed to take a BGA with 420 pins and replace it with a component with 421 pins.
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Whitepaper

Early Die Bump Planning using SiP Layout with EDIS

Learn the process for early IC bump planning and data exchange based on DEF and die abstract using the SiP Layout and Encounter Digital Implementation System (EDIS) environments.
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Whitepaper

Differential Pin Pair Visibility for Logic Assignment and Routing

Learn how to address the challenges in visualizing differential pair information and differential “mates” once there are many of them close together in the design.
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Whitepaper

Addressing the “Power-Aware” Challenges of Memory Interface Designs

This paper assesses how modern tools can be used to address power-aware SI challenges associated with I/O modeling, interconnect modeling, simulation, and analysis.
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