ALS Solves High-Speed PCB Design Challenges with Cadence Sigrity X

ADVANCED LAYOUT SOLUTIONS, the UK’s largest design bureau that specializes in high-speed printed circuit board development, has revolutionized their design process and achieved unprecedented success using Cadence Sigrity Signal Integrity and Power Integrity tools. While bound by non-disclosure agreements that prevent discussing specific client projects, ADVANCED LAYOUT SOLUTIONS’s lead engineer, Chris Halford, shared insights into how Sigrity has transformed their capabilities and results.

“Cadence Sigrity has become an indispensable part of our high-speed PCB design workflow. The comprehensive suite of analysis tools has allowed us to tackle increasingly complex designs with confidence, reducing iterations and time-to-market for our clients.

The ability to simulate and analyse signal and power integrity issues early in the design process has been particularly valuable, helping us to identify and resolve potential problems before they become costly setbacks.

We have access to all the major Sigrity SI and PI tools via the Cadence Sigrity token system – a genius way to access all the Sigrity tools as we wish – each Sigrity tool requires a certain number of tokens to access and once you close the software it releases the tokens to be used on other Sigrity tools.

Knowing that we have access to the latest tools and expert support from Parallel Systems and Cadence, gives us confidence to take on challenging projects and deliver exceptional results for our clients.

The Sigrity suite’s intuitive interface and comprehensive features have empowered our team to push the boundaries of PCB design. We’ve been able to optimize power delivery networks and ensure reliable performance in increasingly dense and high-frequency boards.

Cadence Sigrity tools have not only enhanced our capabilities but also strengthened our reputation as a go-to partner for challenging high-speed PCB projects. We look forward to continuing our success with Cadence as we tackle the next generation of electronic designs.”

Here are some of the key positive features of using the Cadence Sigrity suite:

Early SI/PI problems detected during layout with In-Design Analysis

Power Integrity (PI) Simulation

During the early stages of PCB layout, we frequently utilize PowerDC for simulation purposes. This approach helps me:

• Assess the need for additional layers
• Evaluate the adequacy of the current layer structure
• Optimize copper weights
• Determine if power layer reduction is feasible

These simulations often lead to more efficient designs, sometimes revealing opportunities to use lower copper weights or reduce the number of power layers.

SI Signoff of DDR interfaces using Clarity for 3D extraction of the full interface

For SI signoff of DDR interfaces, a hybrid solver approach is preferred over full 3D extraction. While 3D extraction using tools like Clarity can provide highly accurate S-parameter models, it is far more practical to rely on the workhorse capabilities of the hybrid solver for day-to-day simulations.  However, it is good to know that on very high-speed memory buses or in cases where margins are quite tight, the speed and capacity of a 3D extraction tool like Clarity can be called upon for final signoff.

The hybrid solver method offers a balance of accuracy and efficiency:

1. It considers both non-ideal data signals and the non-ideal power delivery network
2. It allows for rapid analysis and assessment of power-aware SI issues without repeated model extraction
3. It can handle the complexity of DDR interfaces, including high routing density, length matching, spacing, and data signal grouping

This approach is particularly beneficial because:

• It addresses the challenges of large DDR buses with numerous signals, power/ground nets, and decoupling capacitors
• It provides more accurate simulation results that match lab results, while offering a quicker time to market
• It can handle the simulation of hundreds of ports often required in advanced multi-chip DDR interfaces

For final signoff, accuracy remains crucial. However, for most cases, extracting entire memory buses with power and ground in 3D can be relegated to a back plan to the hybrid solver.

The hybrid solver strikes a balance, providing sufficient accuracy for signoff without the computational overhead of full 3D extraction.

However, in extreme cases, a memory efficient and fast 3D solver like Clarity, can step in and provide the extra assurance required to signoff on DDR interfaces.

Via Structure Optimization

We regularly use Clarity to simulate and optimize via structures for high-speed channels early in the design process. This practice ensures that:

• The PCB designer incorporates properly designed, low-loss vias from the outset
• Signal integrity is considered proactively rather than reactively
• Potential issues are identified and addressed early, reducing the need for late-stage interventions

This approach has proven beneficial in enhancing overall design quality and reducing the likelihood of SI-related problems later in the development cycle.

Power Integrity signoff including transient E/T co-simulation using Celsius Thermal Solver

Power integrity signoff is a critical step in the design, particularly for System-on-Chip (SoC) designs. It involves both static and dynamic analysis of the power grid. Static analysis helps identify weak spots in the power network, while dynamic analysis simulates the behaviour of the grid under various operating conditions. IR drop analysis ensures that voltage levels across the chip remain within acceptable ranges, preventing performance degradation or functional failures.

Transient E/T Co-Simulation

Transient E/T co-simulation, enabled by tools like the Celsius Thermal Solver, allows us to:

1. Analyse the dynamic thermal behavior of the chip
2. Identify hotspots and thermal gradients
3. Assess the impact of temperature on electrical performance
4. Optimize the power delivery network for both electrical and thermal considerations

Benefits of Advanced Power Integrity Signoff

1. Improved reliability and performance of SoCs
2. Reduced risk of chip failures due to power-related issues
3. Optimized power delivery network design
4. Enhanced understanding of chip behaviour under various operating conditions

By incorporating transient E/T co-simulation into the power integrity signoff process, designers can achieve a more comprehensive and accurate analysis of their SoC designs, leading to more robust and efficient chips.

Decoupling capacitor optimization of cost vs performance using OptimizePI

Sigrity OptimizePI offers several advantages for decoupling capacitor optimization, balancing cost and performance:

1. Performance optimization: The tool ensures high performance for the power delivery system at both system and component levels
2. Elimination of over-design: The tool helps eliminate unnecessary decaps, reducing over-design for PCBs and IC package
3. Design area recapture: By removing unnecessary decaps, OptimizePI helps reclaim valuable design space
4. Interactive cost vs. performance assessment: Users can interactively evaluate trade-offs between PDS cost and performance
5. Optimization across board/package interface: The tool optimizes PDS across both board and package interfaces.
6. Flexibility: The tool can be configured to maximize performance or reduce decap area without regard for cost, depending on specific needs
7. Time-saving: By automating the optimization process, OptimizePI can significantly reduce PCB development time.

These advantages allow the design team to achieve an optimal balance between decoupling capacitor cost and performance, resulting in more efficient and cost-effective designs.

Multi-board power integrity signoff using SystemPI

Multi-board power integrity signoff using SystemPI is an advanced analysis technique for ensuring proper power delivery across interconnected PCBs.

Key aspects of multi-board PI signoff:

1. Power Delivery Network analysis: Evaluates the entire power distribution system across multiple boards, including VRMs, power planes, and decoupling capacitors
2. DC analysis: Ensures adequate voltage and current delivery to components on all boards
3. AC analysis: Addresses transient current demands and high-frequency power delivery requirements
4. Inter-board connections: Analyses connectors and interfaces between boards for potential PI issues

Power integrity is often overlooked, but it’s critical for high-speed designs. Sigrity’s PI tools have helped us avoid many potential issues that could have led to mysterious signal integrity problems or EMI failures down the line.

Cadence Sigrity has been a key factor in our growth and success. It has allowed us to differentiate ourselves in the market and deliver superior results for our clients. We consider it an essential tool for any serious high-speed PCB design team.

Chris Halford – Advanced Layout Solutions

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