How to Design RF PCBs: Layout, Stackup, and Signal Integrity Best Practices

Radio frequency (RF) printed circuit boards (PCBs) operate in a regime where standard digital layout rules simply stop working. The PCB industry classifies any high-frequency board operating above 100 MHz as an RF PCB, with anything above 2 GHz entering microwave territory. At those frequencies, a trace isn’t just a conductor; it’s a transmission line with characteristic impedance, propagation delay, and loss behavior that must be engineered explicitly.

The core design challenges fall into three areas:

• Signal attenuation: Energy lost through the substrate as heat, increasing with frequency
• Impedance mismatch: Reflections caused by geometry changes that degrade signal fidelity
• Noise and electromagnetic interference (EMI) coupling: Unwanted energy transfer between RF and digital domains

Get any one of these wrong and the board fails, often in ways that aren’t obvious until you’re staring at a spectrum analyzer, wondering where your signal went. In this article, we’ll review how to design RF PCBs.

Why Substrate Choice Defines Your Design’s Ceiling

Material selection is the first and most consequential decision in RF PCB design. Standard FR-4 has a dielectric constant (Dk) around 4.5 and a dissipation factor (Df) around 0.02 — adequate up to perhaps 1–2 GHz for short runs, but increasingly lossy beyond that. As frequency rises, FR-4’s dielectric constant can shift by up to 10%, causing impedance fluctuations across PCB traces. That kind of instability is fatal to a controlled impedance design.

For serious RF work, purpose-built laminates are the answer. Two parameters drive the selection:

• Dk (dielectric constant): Controls signal propagation speed and trace geometry for a target impedance. Lower Dk means wider, more manufacturable traces.
• Df (dissipation factor): Quantifies how much signal energy converts to heat in the dielectric. At microwave frequencies, even small differences in Df translate directly into insertion loss.

Common RF PCB Substrate Materials

RO4350B has a Dk of 3.48 ± 0.05 measured at 10 GHz, but Rogers recommends using a “design Dk” of 3.66 for impedance calculations to account for copper foil roughness effects. Use the material Dk, and you’ll cut your traces too narrow. RO4350B uses a proprietary woven glass-reinforced hydrocarbon/ceramic formulation that provides tight Dk control and low loss, while using the same processing methods as standard epoxy/glass. It does not require the specialized through-hole treatments that PTFE-based materials demand.

PTFE-based RT/duroid 5880 pushes further, with Df near 0.0009, making it suitable for the millimeter-wave bands. The tradeoff is cost and fabricability: these materials are significantly more expensive and require specialized fabrication processes. For cost-sensitive mixed designs, outer layers can use high-grade Rogers laminates while inner layers use less expensive epoxy-glass, a hybrid stackup approach that balances performance and economics.

Stackup Design and Controlled Impedance

Every layer in your stackup is a variable in the impedance equation, which is why stackup planning happens before routing, not after. The target for virtually all RF transmission lines is 50 ohms. From a physics standpoint, 50 ohms represents a middle ground: maximum power handling in coaxial cable occurs at approximately 30 ohms, minimum signal attenuation near 77 ohms, and 50 ohms is the practical sweet spot between the two. A well-matched design is simpler to execute because IC manufacturers, attenuator vendors, and antenna suppliers all build their components for 50 ohms, and PCB layout becomes more straightforward because so many engineers share that same goal.

Calculating and Enforcing 50-Ohm Geometry

You achieve 50-ohm transmission lines by calculating the trace width against three variables: copper thickness, dielectric thickness, and the material’s Dk. Adjust any one of those without recalculating the others, and your impedance shifts.

Structural rules to enforce during stackup design:

• Use microstrip or stripline topologies: Microstrip places RF traces on outer layers for easier component mounting; stripline buries them between ground planes for better shielding. Choose based on isolation requirements.
• Dedicate Layer 2 as a solid ground plane: This gives top-layer RF components the shortest possible return path, minimizing parasitic inductance.
• Manage dielectric thickness carefully: Too thin and the required 50-ohm trace width becomes too narrow to fabricate reliably; too thick and radiation increases.

RF Trace Routing and Domain Isolation

Physical layout is important when designing RF PCBs, as it directly sets the characteristic impedance but can also break it. Firstly, avoid right-angle bends. At microwave frequencies, 90-degree corners behave as capacitive discontinuities, so use 45-degree chamfered bends or gentle curves instead. Every bend, via, and width change is a potential reflection source.

Keep RF traces as short as physically possible. A signal at 1 GHz has a wavelength of roughly 30 cm in free space, and shorter in a dielectric. Just a few centimeters of unnecessary trace can introduce measurable phase delay and loss, both of which compound as frequency rises.

Routing and isolation guidelines:

• Eliminate sharp corners: Use arcs or 45-degree chamfers for any direction change. The bend radius should exceed three times the trace width to ensure characteristic impedance remains unchanged through the curved segment.
• Hard-separate RF and digital domains: Never allow digital return currents to flow beneath RF signal traces. The ground return current for an RF signal flows in a narrow band directly beneath and alongside the signal trace. Anything that disrupts this return path forces the current into a wider, more inductive loop.
• Isolate transmit and receive paths: In transceiver designs, the transmit path carries high power levels that can saturate or damage the receive chain if they couple back. Physical separation, shielding, and careful filtering at the boundary are all necessary.
• Plan for shielding cans: For production RF designs, metal shielding enclosures over sensitive blocks, such as low-noise amplifier (LNA) stages, voltage-controlled oscillator (VCO) circuits, and synthesizers, dramatically reduce spurious emissions and improve isolation between functions.

Grounding, Via Strategy, and EMI Control

Grounding is where RF designs most commonly fail. A poorly designed ground structure introduces parasitic inductance that immediately manifests as noise, electromagnetic interference (EMI), and degraded isolation between circuit blocks.

Via stitching is the primary technique for creating a low-impedance connection between ground layers and containing signal energy within defined boundaries. Placing stitching vias along the perimeter of RF sections creates a Faraday cage effect that blocks noise coupling between domains; learn how to generate via shielding and shield RF signals in OrCAD. However, this shielding strategy introduces an unavoidable physical catch. Vias are discontinuities: every layer transition through a via introduces parasitic inductance in the barrel and parasitic capacitance from the pads. This is irrelevant at low frequencies, but a source of reflections and loss at microwave frequencies.

Ground plane and via rules to implement before finalizing layout:

• Apply the λ/20 spacing rule: Space stitching vias at no more than one-twentieth of the wavelength (λ) of the highest operating frequency. For a 5 GHz signal, λ/20 in a typical PCB dielectric is approximately 3 mm.
• Give each ground pin its own via: Do not daisy-chain ground connections. Each decoupling capacitor and component ground pin needs a dedicated, direct path to the ground plane.
• Never route RF traces over ground plane gaps: A slot or cutout in the reference plane beneath an RF trace forces the return current into a large inductive loop, which is exactly the kind of discontinuity that generates EMI and degrades isolation.
• Back-drill signal vias above 10 GHz: Where vias are unavoidable on RF signal paths, back-drilling removes the unused stub below the transition layer. Without it, the stub acts as a shorted quarter-wave resonator, creating a passband notch at the worst possible frequency.

How to Design RF PCBs Checklist and FAQ

Checklist Before Sending to Fab

• All RF transmission lines calculated for 50 ohms using the fabricator’s specific material Dk — and the design Dk, not the raw material Dk, if using RO4350B
• Dielectric material (RO4350B, RT/duroid 5880, or equivalent) confirmed as rated for the maximum operating frequency
• No digital routing crossing over or under RF signal return paths
• Via stitching spacing verified at λ/20 for the highest frequency present
• All RF traces use curved or 45-degree chamfered corners, no 90-degree bends
• Transmit and receive paths are physically separated and filtered at their boundary
• Back-drilling is specified for any signal vias in designs above 10 GHz

Frequently Asked Questions

Why is 50 ohms the standard RF impedance?

It’s a physics-driven compromise. Maximum power handling in coaxial cable occurs at approximately 30 ohms; minimum signal attenuation occurs near 77 ohms. Fifty ohms lies between both, providing a sweet spot for high-power transmission while keeping signal loss reasonably low. The deeper reason it persists: a well-matched design is vastly simpler to execute because manufacturers of ICs, fixed attenuators, antennas, and similar components build their parts with 50 ohms in mind.

Can I use FR-4 for an RF PCB?

FR-4 is adequate up to perhaps 1–2 GHz for short runs but becomes increasingly lossy beyond that. Above that threshold, the combination of high Df and an unstable Dk makes impedance control unreliable. If your design exceeds 2 GHz or involves long RF traces, a purpose-built laminate such as RO4350B or RT/duroid 5880 is the right choice.

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