Today’s PCB designers must create increasingly complex boards and systems which contain high-speed interfaces. Utilizing a constraint-driven design approach can help manage the additional complexities of high-speed designs and interfaces. Leveraging constraint sets for DDR in Allegro X simplifies this process with advanced routing tools that help speed up the routing of high-speed signals and enable PCB designers to rapidly route and verify complex bus structures.

In this webinar, you will learn how you can leverage constraint sets for DDR to:

• Define impedance requirements through the Cross Section Editor
• Use Constraint Sets (CSets) to apply rules to bus structures (DDRx) quickly
• Leverage Timing Vision to route signals
• Use auto-interactive delay tuning to verify compliance with constraints