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Setting Analysis Options and Timing Budget for Power-Aware Parallel Bus

Learn how to configure a timing budget and simulation analysis options for power-aware DDR analysis with Sigrity.
Duration: 00:06:45

For an accurate analysis of DDR4, it is very important to incorporate the Power Delivery Network into the simulation and analyze the effect of noise due to switching of the parallel bus signal groups.

In this series of videos, we’ll learn how to model, simulate, and analyze a Power-Aware Parallel Bus System with Sigrity. In part 4 of this video series, we will teach you how to:

  • Setup timing budget parameters
  • Configure Simulation Analysis options
  • Configure On die package parasitics for the controller and Memory

Follow along with these demo files: https://www.ema-eda.com/wp-content/uploads/2023/05/2023PAPBS_Part4.zip

This is part 4 of this video series:

Learn how to model a simple parallel bus system here.

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