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Circuit Simulation and Analysis of a Power-Aware Parallel Bus

Learn how to perform power-aware signal integrity analysis for DDR4, analyze the simulation results and generate a report with Sigrity.
Duration: 00:06:09

For an accurate analysis of DDR4, it is very important to incorporate the Power Delivery Network into the simulation and analyze the effect of noise due to switching of the parallel bus signal groups.

In this series of videos, we’ll learn how to model, simulate, and analyze a Power-Aware Parallel Bus System with Sigrity. In part 5 of this video series, we will teach you how to:

  • run a time domain circuit simulation of DDR4 power-aware parallel bus system
  • analyze the simulation
  • generate a report

Follow along with these demo files: https://www.ema-eda.com/wp-content/uploads/2023/05/2023PAPBS_Part5.zip

This is part 5 of this video series:

Learn how to model a simple parallel bus system here.

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