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Setting up Timing Budget and Analysis Options for SPBS: Part 1

Learn how to setup the required timing budget to perform DDR simulation in Sigrity.
Duration: 00:03:15

A simple parallel bus system (SPBS) is one in which data is transferred between components using multiple parallel communication lines, such as DDR4 and DDR5. In this video, learn how to setup the required timing budget and simulation analysis options before analyzing the topology (part 6 of 10). Sigrity allows you to run circuit or channel simulation for a parallel bus system. In this video, you will:

  • Load a project file
  • Configure a timing budget
  • Define read and write parameters
  • Save a project

Learn more about how Sigrity can help you simulate and verify interface operation and follow along with the demo files here.

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