Resource Library
Posted on Mar 18, 2019
BOM denied. Redesign required. Dreaded words to any engineering team. Obsolete parts, RoHS / REACH compliance issues, inadequate stock, almost every engineer has been bitten by one of these issues at some point. Fortunately, it doesn’t have to be this way. Join EMA Design Automation and SiliconExpert to learn about the common causes of BOM rejection and how to prevent these issues in the future. As they say an ounce of prevention is worth a pound of cure.
Posted on Feb 27, 2019
With all the pressures engineers face to make everything ‘better, faster, cheaper, smaller’ all in less time managing your design data can seem like the least of your concerns. However, data management issues can sink a project just as fast as any design flaw. Effectively managing your design data is a critical piece to ensuring overall project success. Get critical design data management tips and best practices learned the hard way so you don’t have to from the experts at EMA and xPLM.
Posted on Nov 20, 2018
An overview of BER Analysis for DDR4 Interfaces with SystemSI
Posted on Nov 2, 2018
Connect with the world's leading manufacturers to easily request and implement custom manufacturability rules. Learn more.
Posted on Nov 2, 2018
Double check your DFM rules before signoff with a forced batch check of all rules for your whole design. If you do find something awry, it’s easy to locate and fix in your design.
Posted on Nov 2, 2018
Double check your DFM rules before signoff with a forced batch check of all rules for your whole design. If you do find something awry, it’s easy to locate and fix in your design.
Posted on Nov 2, 2018
Easily ensure test points are accessible in your designs.
Posted on Nov 2, 2018
Check for common copper and component spacing issues that could potentially derail manufacturing and cause a respin.
Posted on Nov 2, 2018
Easily create and assign constraints for manufacturing based on IPC standards and common PCB rules.
Posted on Nov 2, 2018
Remove unused sections of plated through holes in high-speed designs to improve signal integrity on your designs.
Posted on Nov 2, 2018
Measure from true signal origin to end point through vias and through packages, not just the etch, so you can get timing right and ensure signal performance.
Posted on Nov 2, 2018
Visual indicators of length constraints help you meet delay propagation and total etch length goals when placing components.
Posted on Nov 2, 2018
Real-time interactive checks help you easily find and fix common route quality issues that manufacturing DRC signoff checks miss.
Posted on Jul 31, 2018
Manually adding fillets and teardrops can add weeks to your design. And allowing a board house to add them after design completion, will leave you unaware of effects on your board. By automating this process and adhering to predefined constraint rules, you can save time and ensure your design intent is unchanged. OrCAD helps you do this with Dynamic Shape Fillets. Simply set the required parameters for the teardrops or fillets. Highlight the selection of pins or vias and OrCAD PCB Designer automatically creates the shapes.
Posted on Jul 31, 2018
Running traces over voids and split planes can cause impedance and noise control issues. Signal traces must be routed over an uninterrupted copper plane to ensure continuous loop or return path current. However, by automatically identifying problem traces, you can eliminate the need for time consuming, error-prone manual scanning on every layer of the board. OrCAD helps you do this with Segment Over Void detection. Now, problem traces are reported with the click of a button and highlighted for your review.
Posted on Jul 31, 2018
Resolving length matching issues can be difficult and time consuming, especially on densely populated boards when space is in high-demand. However, by automating this process you can save time and focus on other aspects of the design. OrCAD Interactive Delay Tuning can help. A real-time pop up meter allows you to see when the required trace length has been achieved. Choose from sawtooth, trombone, or accordion. Select the trace and watch the meter as the delay tune is added. The meter will turn green when the desired length is met. Save time and money with Interactive Delay tuning in OrCAD PCB Designer.
Posted on Jul 31, 2018
Matching trace lengths for large-bit buses and differential pairs in your design is vital. However, this can be a tedious process and mismatched lengths can result in signal quality and integrity issues. Signals may need to be synchronized with clocks and unmatched differential pairs create additional noise. Any of these issues can be detrimental to your design. However, by automating the process you can improve signal quality and reduce time and errors, allowing you to focus on more important aspects of the design. OrCAD helps you do this with constraints for Net Groups. Create Constraints for minimum and maximum propagation delay in mils, nanoseconds or percentage. Or set constraints for total etch length. Create Net Groups and assign the constraints to all the nets in a group. Analyze the constraints without ever leaving the Constraint Manager. DRC Markers flag any incorrect lengths in real-time. Eliminate the need to check each individual net with OrCAD PCB Designer.
Posted on Jul 24, 2018
Getting arcs equally spaced when routing a bus around a curved, flex circuit is not easy. With routing software offering a grid-based approach, this often leads to sloppy spacing and inadequate contour routing. However, with OrCAD contour etch routing, the software understands you are routing a bus with a unique contour and gives you the ability to specify the spacing between each one. This allows it routes to be completed uniformly and correctly spaced, all while performing DRC checks along the way to ensure you are adhering to set rules.
Posted on Jul 2, 2018
Flex PCB design has many advantages. In fact, the global market for flex/rigid-flex boards more than doubled in the past 4 years alone. Along with those benefits come new design challenges that weren’t present in “standard” 2D PCBs. Learn about common flex design issues and how to design to help you catch them before they become a problem. Become a flex PCB design master with tips from the experts at EMA in this webinar.
Posted on Jun 13, 2018
Prevent time-to-market delays by identifying manufacturing issues before they become a costly mistake. It’s not uncommon for designs to be submitted to manufacturing only to have problems identified that require design reworking and re-submission. This results in lost production time, schedule delays, and recurring tooling costs. What if you could identify DFM problems as you design and fix them when they happen? This webinar will help show you how to spot and fix troublesome DFM issues in-design before they ever become a problem.