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New in Allegro 17.2-2016 – Dynamic Concurrent PCB Design Technologies

Globally dispersed design teams are becoming more common, which compounds the challenge of shortening design cycle times. Manual workarounds that address multi-user issues are time consuming, slow, and prone to error. The new Cadence® Allegro® dynamic concurrent-team-design capability focuses on shortening the largest portion of the PCB layout design cycle. It provides dynamic concurrent PCB team design for multiple designers to work on the same design at the same time without any set-up requirements. In addition, new features—including interactive etch-editing capabilities, Allegro TimingVision™ technology, Auto-interactive Phase Tuning (AiPT), and Auto-interactive Delay Tuning (AiDT) capabilities—provide proven time reductions to route advanced high-speed interfaces such as DDRx and PCI Express® (PCIe®) by up to 80 percent.

Allegro PCB Designer provides two ways—Concurrent Team Design and Design Partitioning—for multiple designers to work concurrently on the same design for faster time to market and reduced layout time.

Concurrent Team Design

The first option is to use Allegro PCB Concurrent Team Design Option, which allows multiple users to work on the same design without having to split (partition) the design. By connecting users to a common Allegro database, this simple approach allows multiple PCB designers to easily work on the design at the same time, and any changes made on their canvases are reflected on the server and seen by other users.

The Concurrent Team Design capability that allows users to work on the same design provides two easy-to-use modes. The informal mode allows an initial user to start the concurrent process, with additional users able to join or leave at any time after that. A more structured approach allows users to set up a server where the design can reside. After this one-time setup, all users can join or leave at any time.

Design Partitioning

The second option, Allegro PCB Design Partitioning Option, allows users to work on individual sections of a design exported from a master design. Partitioning a design into multiple sections or areas for layout and editing by several design team members can accelerate the time to complete the layout process. Designs can be partitioned vertically (sections) with soft boundaries or horizontally (layers). As a result, each designer can see all partitioned sections and update the design view for monitoring the status and progress of other users’ sections.

Design Partitioning vs. Concurrent Team Design

Allegro PCB Concurrent Team Design technologies support the following Allegro PCB Editor features including TimingVision™ and interactive etch-editing capabilities, so you can work synchronously together to improve overall productivity and reduce design cycles.


Allegro TimingVision™ technology provides an innovative and unique environment that allows designers to see real-time delay and phase information right on the routing canvas. With the embedded route engine, the Allegro TimingVision environment provides real-time feedback during interactive editing and enhances the designer’s ability to develop a strategy for resolving timing on large buses or interfaces such as DDRx and PCle Gen3. Coupled with AiPT and AiDT capabilities, this environment shortens timing closure of high-speed PCB interfaces by up to 75 percent.

Interactive Etch-Editing Capabilities

Interactive etch-editing capabilities enable real-time, shape-based, any-angle, push/shove routing, which now includes improved arc route handling. It allows designers to view a real-time, graphical heads-up display of how much timing slack remains for an interconnect that has high-speed constraints. Interactive routing also enables diff pair and group routing on multiple nets and interactive tuning of nets with high-speed length or delay constraints. Users can shorten the time to route designs using the Concurrent Team Design capability using interactive etch-editing commands as well as AiPT and AiDT capabilities as well as dynamic shape voiding during routing.

Want more information on Allegro PCB Concurrent Design?
For technical details or a demonstration, please contact us.

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