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Posted on Sep 27, 2016
Cadence Sigrity and EMA TimingDesigner have teamed up to provide an fully integrated flow to achieve DDR timing sign-off. Sign-Off with confidence using the industry leading accuracy of Sigrity power-aware simulation with the advanced timing diagram driven visualization and analysis environment of TimingDesigner
Posted on Sep 20, 2016
EMA Enterprise Connect enables seamless integration between your PCB design environment and the PLM, MRP, ERP systems driving overall product development and management.
Posted on Sep 12, 2016
See how EMA Enteprise Integrate enables a seamless bi-directional integration with Oracle Agile PLM including native menus inside the OrCAD user interface.
Posted on Sep 9, 2016
Allegro Sigrity SI Base and Power-Aware SI Option from Cadence are demonstrated. Sigrity technologists guide you step by step on how to utilize power-aware electric rule checks to confidently fast track the sign off process for your PCB designs.
Posted on Sep 7, 2016
PCB Editor 17.2 includes the latest 3D rendering technology for fully realistic 3D views of your design. Upgraded capabilities also include 3D interference checking and cross probing between 3D and 2D views.
Posted on Jun 24, 2016
See the many improvements have been made to the backdrill process in Allegro PCB Designer to assist the PCB designer in managing the backdrill vias/padstacks, route around the backdrill vias/padstacks with accurate DRCs, and real-time feedback.
Posted on Jun 24, 2016
Take a look at some of the enhancements added to Allegro PCB Editor in the 17.2-2016 release including tabbed routing, return path management, and enhanced arc and contour routing.
Posted on Jun 17, 2016
Allegro® Package Designer and Sigrity™ XtractIM™ technology from Cadence are demonstrated. Sigrity technologists guide you step by step on how IC Package Designers can conveniently identify electrical problems throughout the design cycle. Following this methodology, experts are enabled to focus on the difficult problems without getting overloaded and design cycles times are reduced.
Posted on Jun 17, 2016
Learn about Allegro Sigrity SI Base and the new flow planning feature for route planning with signal integrity analysis through a brief demonstration. Sigrity technologists guide you discover many signal integrity problems as soon as a PCB design has been placed. The methodology enables finding and fixing many signal integrity concerns without having to rip up and re-route a design.
Posted on Jun 17, 2016
Learn about Allegro Sigrity SI Base and the System Serial Link Analysis Option through a demonstration. Sigrity technologists guide you step by step on how to model serial link interfaces using a cut-and-stitch methodology. The methodology enables creation of 3D full-wave accurate s-parameter models 10 times faster than traditional approaches.

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