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Posted on Nov 11, 2016
Sigrity technologists guide you step by step on how to use the Sigrity Finite Difference Time Domain (FDTD) simulator to accurately predict the impact of simultaneous switching noise (SSN) in a system context. A PCB layout is directly connected to a system topology without having to perform an S-parameter extraction. This “FDTD-direct” methodology overcomes the challenge faced by SI engineers who fear accuracy could be compromised when converting an S-parameter to a simplified broadband spice model.
Posted on Nov 9, 2016
Eliminate manual tedious and error prone manual part creation. Instead of spending hours manually building PCB symbols and footprints, access millions of parts directly within the OrCAD environment.
Posted on Nov 7, 2016
See how the Allegro 17.2-2016 PCB design software handles the unique challenges associated with rigid-flex designs.
Posted on Oct 21, 2016
PCB design is a never-ending cycle—the sooner you can finish one design, the sooner you can get started on the next. Join our webinar and learn how the latest advancements in Cadence® PCB 17.2-2016 technology can help you.
Posted on Oct 20, 2016
Ensure your parts will be correct, available, and in compliance with access to deep supply chain insights available across 300+ million devices.
Posted on Oct 7, 2016
Sigrity technologists guide you step by step on how to setup a leadframe package design for accurate extraction using the 3D quasi-static solver engine. Accurate RLC extraction is performed on a leadframe design from the same environment used to model multi-layer packages with other solver engines. Design productivity is improved by enabling a common environment to model leadframe, flip-chip, and wirebond IC Packages.
Posted on Sep 30, 2016
OrCAD PCB Productivity Toolbox provides a comprehensive suite of utilities to help PCB designers to increase PCB layout productivity. This short video will show you a selection of features including Label Tune, Barcode, Polar Grid and Post Processing.
Posted on Sep 30, 2016
OrCAD DFM Checker provides comprehensive PCB manufacturing analysis, Hierarchical Rule-Set-Driven-Analysis, and Error Charts.
Posted on Sep 27, 2016
Cadence Sigrity and EMA TimingDesigner have teamed up to provide an fully integrated flow to achieve DDR timing sign-off. Sign-Off with confidence using the industry leading accuracy of Sigrity power-aware simulation with the advanced timing diagram driven visualization and analysis environment of TimingDesigner

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