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Posted on Nov 2, 2018
Check for common copper and component spacing issues that could potentially derail manufacturing and cause a respin.
Posted on Nov 2, 2018
Easily create and assign constraints for manufacturing based on IPC standards and common PCB rules.
Posted on Nov 2, 2018
Remove unused sections of plated through holes in high-speed designs to improve signal integrity on your designs.
Posted on Nov 2, 2018
Measure from true signal origin to end point through vias and through packages, not just the etch, so you can get timing right and ensure signal performance.
Posted on Nov 2, 2018
Visual indicators of length constraints help you meet delay propagation and total etch length goals when placing components.
Posted on Nov 2, 2018
Real-time interactive checks help you easily find and fix common route quality issues that manufacturing DRC signoff checks miss.
Posted on Oct 19, 2018
Routing DDR and high-speed bus interfaces can be one of the most daunting tasks in your design. With the new bus designer, all you need to do is simply describe the bus you are trying route and Constraint Manager for OrCAD will handle generating the appropriate constraints automatically.
Posted on Oct 19, 2018
Remove unused sections of plated through holes in high-speed designs to improve signal integrity on your designs.
Posted on Oct 19, 2018
Easily meet length and phase pin-to-pin constraints as traces bend without creating electrical issues.
Posted on Oct 19, 2018
Easily and quickly identify impedance discontinuity issues visually, without simulation models or extensive signal integrity expertise.

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