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Posted on Mar 14, 2016
As designs become more complex and project timelines more compressed, it’s important to identify opportunities to enhance current design processes. MakeCAP Power integrates with the Cadence® high-speed PCB design flow to easily embed high-speed properties into Cadence OrCAD® Capture schematics in a fraction of the time.
Posted on Mar 14, 2016
The Power IC Model Library incorporates over 400 high fidelity timedomain PSpice models for power electronic designs. It gives designers capabilities previously unavailable for many popular parts - the ability to plug in a model, representative of the actual IC, and simulate the switching performance under actual operating conditions.
Posted on Feb 25, 2016
Founded by the National Society of Professional Engineers (NSPE) in 1951, National Engineers Week has been a way to increase understanding and interest of careers in the engineering and technology fields for 65 years.
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Posted on Feb 19, 2016
Partitioner mode. Pins selected and highlighted in the spreadsheet can easy be moved to the graphic symbol with these commands.
Tags: video, video, Other
Posted on Feb 19, 2016
Part 2 of 2, this video provides an overview of the Footprint Builder as a standalone tool of EDABuilder. It demonstrates customizing a D micro connector template to match the vendor datasheet.
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Posted on Feb 19, 2016
Part 1 of 2, this video provides an overview of the Footprint Builder as a standalone tool of EDABuilder. It demonstrates the many advanced features of creating either IPC calculated footprints or User and Vendor defined land patterns.
Tags: video, video, Other
Posted on Feb 19, 2016
This training video demonstrates the use of the spread sheet interface to import a variant or random grid BGA or Grid Array. The Generator / Calculator is use to automate the basic outline information. A vendor supplied pin assignment spread sheet is imported and back annotated to the original array.
Tags: video, video, Other
Posted on Feb 19, 2016
This video demonstrates the EDBuilder flow of building and verifying a TI Microcontroller part including a fractured symbol set and PCB Footprint/Land model all completed in less than 12 minutes.
Posted on Feb 19, 2016
Drawing Basic Timing diagrams.

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