As signal speeds continue to increase and operating margins become smaller, maintaining signal integrity has become one of the most critical challenges in modern PCB design especially as data rates continue to increase in interfaces such as DDR, PCIe, USB, HDMI, and MIPI. Among the various signal integrity issues engineers face, signal reflections remain one of the most common and potentially disruptive problems. Understanding the root causes of reflections and their impact on system performance is essential for developing robust high-speed designs.
What Are Signal Reflections?
Signal reflections occur when part of a high-speed signal is “reflected” back towards the source. Signal reflections can produce several problems, including:
Ringback
Ringback describes the oscillations on a signal waveform after a transition and before the signal settles into the high or low state.
Overshoot
Regardless of which type of crosstalk your design may be exhibiting, it is important to be aware of these effects, understand how to measure the impact, and assess mitigation strategies if needed.
Overshoot describes the peak or trough of a signal waveform after a transition in relation to its high or low state. The peak of a waveform after a rising edge is called high overshoot, and the trough of a waveform after a falling edge is called low overshoot or undershoot. Overshoot is a common feature when feedback is used for error correction, however, it is undesirable for filtered signal processing.
Propagation Delay
Propagation delay is defined as the amount of time between transmission and reception. In parallel digital circuits, the propagation delay should be approximately the same for all data bits to ensure they remain synchronized.
Minimum First Switch Time
Minimum First Switch time is defined as the time between the beginning of driver transition and the receiver crossing the low voltage threshold (if the driver is rising) or the receiver crossing the high voltage threshold (if the driver is falling).
In other words, it is the time between the transmitter beginning to rise or fall and the receiver voltage crossing the low voltage threshold if rising or high voltage threshold if falling.
Maximum Final Settle Time
Maximum Final Settle time is defined as the time between the beginning of the driver transition and the receiver crossing the high voltage threshold (if the driver is rising) or low voltage threshold (if the driver is falling) for the last time before settling.
In other words, it is the time between the transmitter beginning to rise or fall and the last crossing of the low voltage threshold if falling or high voltage threshold if rising at the receiver end.
How to Measure Signal Reflections
Signal reflections can affect overall system performance and negatively affect signal quality. To comprehensively analyze signal reflections, several waveform parameters must be measured and calculated. These include:
| Measurement | Importance |
|---|---|
| Ringback Margin | Ringback can be used to identify signal quality issues, such as reflection along a transmission path due to impedance mismatch. |
| Overshoot | Analyzing overshoot provides a good indication of signal quality, as any issues are usually indicative of excess noise accompanying the signal, either from the source or along the channel. |
| Propagation Delay | If the transition of each data net is not complete before the clock net transition, the receiver may read incorrect data, causing undesired operation. |
| Minimum First Switch | Minimum first switch time can be used to determine overall slew and ensure equal timing on all nets. |
| Maximum Final Settle | If the length of this time exceeds the clock period, the data read by the receiver won’t be accurate. |
Ringback Margin
Ringback margin measures the difference of the ringback peak from the high or low threshold. Ringback margins should be calculated for both high and low logic levels for each signal of the bus.
To calculate the High Ringback Margin, locate the lowest point after the initial 0 to 1 signal transition when the signal has moved through the VILdcMax, VILdcMin, and VILacMin positions. Measure the voltage difference between this lowest signal point and VIHdcMin.
To calculate the Low Ringback Margin, locate the highest point after the initial 1 to 0 signal transition when the signal has moved through the VIHdcMin, VILdcMax, and VILacMax positions. Measure the voltage difference between VILdcMax and this highest signal point.
Additionally, the time at which ringback occurs must be analyzed. If ringback occurs before the specified Tac time point, where the device has seen the signal above the VIH(ac)Min or below the VIL(ac)Max values for the proper amount of time, it will result in a compliance failure.
Acceptable Values of Ringback:
For acceptable ringback, the ringback margin should be greater than 0mV and occur after the defined Tac time point. This means the high ringback and low ringback should not surpass the VIH(dc)Min and VIL(dc)Max values respectively.
Overshoot
Both the maximum overshoot amplitude and the overshoot area should be evaluated.
Maximum Overshoot: Measure the maximum amplitude of the signal above VDD.
Overshoot Area: The overshoot area can be calculated by:
0.5 × Overshoot Amplitude (V) × Overshoot Width (ns)
Acceptable Value of Overshoot:
The maximum amplitude and overshoot area is the amount of over-voltage the device can take without damage. These values can be obtained from the device datasheet.
Propagation Delay
Propagation delay can be measured by measuring the difference in timestamps between when the transmitted signal starts to rise or fall and when the receiver signal starts to follow.
Acceptable Values of Propagation Delay:
The propagation delay of a signal should be entirely within its clock period. Propagation delays of signals in a group should be relatively consistent with each other.
Minimum First Switch Time
To measure Minimum First Switch Time, determine the time at which the transmitted pulse starts to change state and subtract that from the last time the receiver pulse crossed the low input (if rising) or high input (falling) voltage.
Acceptable Values of Minimum First Switch Time:
The Minimum First Switch Time will always be greater than or equal to the Propagation Delay. Lower values are recommended as a shorter switch time is less likely to result in incorrect data reception.
Maximum Final Settle Time
To measure Maximum Final Settle Time, determine the time at which the transmitted pulse starts to change state and subtract that from the last time the receiver pulse crosses the high input (if rising) or low input (falling) voltage before settling.
Acceptable Values of Maximum Final Settle Time:
The Maximum Final Settle Time should fall well within the clock period and be relatively consistent for all data nets in the design. The settle time for data nets should also be less than that of the clock net, otherwise the clock pulse may be interpreted before any data pulses have finished settling.
Common Causes of Signal Reflections
Signal reflections occur when a portion of an electrical signal traveling along a trace is reflected back towards the source, typically after encountering a discontinuity or impedance mismatch. Signal reflections can arise from various factors throughout the PCB layout. The table below will help to identify the cause of the reflections, why signal reflections occur, and a solution to help PCB designers identify and correct signal reflections.
| Cause | Problem | Solution |
|---|---|---|
| Impedance Discontinuities | Signal energy is reflected back toward the source, causing overshoot, undershoot, and waveform distortion. | Impelement impedance matching and controlled impedance. |
| Improper Termination | Excessive ringing, multiple signal transitions, and reduced noise margins. | Add appropriate termination (series, parallel, Thevening or AC) based on the interface requirements. |
| Trace Wdith Changes | Sudden impedance changes generate localized reflections and degrade signal integrity. | Develop a routing strategy to keep widths consistent. |
| Via Transitions | Via inductance and capacitance create impedance discontinuities, especially at high frequencies. | Optimize via design and minimize via usage. |
| Stubs | Unused trace branches act as resonators that reflect energy back into the main signal path. | Develop a routing strategy which eliminates unused stubs and shorten branch lengths. |
| Poor PCB Stackup Design | Inconsistent impedance and increased sensitivity to manufacturing variations. | Design PCB Stackups with controlled dielectric thickness and impedance targets. |
Understanding Impacts from Signal Reflections
Once signal reflections occur, their effects can propagate throughout the entire signal channel, degrading waveform quality, reducing timing margins, and ultimately impacting overall system performance. Understanding how reflections influence both analog and digital signals is essential for identifying potential reliability issues and implementing effective mitigation strategies:
- Distortion
Signal reflections distort the shape of the signal which can lead to inaccurate signal transmission and reception.
- Ringing
Reflections cause ringing (where the signal oscillates at the transition edges) which can lead to misinterpretation of the signal.
- Jitter
Reflections can lead to timing variations or jitter in digital signals which can disrupt the synchronization of digital circuits.
- Overshoot and Undershoot
Reflections can cause the signal to exceed or drop below the normal levels or operation, potentially damaging components and causing incorrect logic levels.
- Degraded Eye Diagrams
Reflections can degrade the quality of eye diagrams which have a higher likelihood of data errors due to poor signal transitions and timing.
- Bit Errors
Reflected signals can degrade signal quality and result in bit errors or communication failures in high-speed systems.
- Signal Skew
Signals may experience different delays due to reflections, leading to signal skew and timing mismatches between different signal paths.
To prevent these issues, PCB designers must try to minimize signal reflections through mitigation strategies.
Mitigation Strategies for Signal Reflections
Signal reflections must be addressed to improve signal quality in your PCB designs, ideally throughout the PCB design process when change is easiest to implement. To mitigate signal reflections, the following strategies can be utilized:
1. Perform Impedance Matching
Ensure that traces are designed with controlled impedance to match the source and load. If needed, use termination resistors to match the impedance and absorb reflection.
- Design for Controlled Impedance
- Include Proper Termination
2. Develop a Routing Strategy
Avoid making sharp bends when routing. Use smooth curves with 45° bends instead. With high-speed signal traces, avoid stubs or branches. Maintain uniform impedance by keeping trace width and thickness the same.
- Avoid Sharp Bends
- Minimize Stubs
- Deploy uniform width and thickness
3. Follow PCB Stackup Guidelines
Use PCB materials with consistent dielectric properties and for designs with controlled impedance, be sure to provide detailed information to your manufacturer and allow for minor adjustments to the stackup, trace width, and trace spacing to meet your impedance requirements.
- Use Controlled Dielectric Properties
- Allow Manufacturing Adjustments
4. Optimize Via Usage
Via transitions will affect the impedance of traces; therefore, you should avoid using an excessive number of vias, especially in high-speed signal paths. If vias are necessary, incorporate backdrilling to remove unused portions and prevent reflections.
- Reduce Via Transitions
- Use Backdrilling
Implementing these mitigation strategies throughout the PCB design process can result in many benefits and allow you to set the design up for success. But identifying the signal reflections may be difficult and time-consuming. How do you know when and where to deploy these mitigation strategies?
Incorporating Simulation
To identify where additional mitigation is needed in your PCB design, simulation can be deployed to quickly pinpoint signal reflections. Simulation can be used to analyze signal integrity and identify signal reflections created by:
- Changes in trace widths
- Impedance discontinuities
- Improper trace termination
- Via transitions
- Stubs
Once these issues are identified, mitigation strategies can be incorporated into the PCB design to improve signal quality.
Why Should You Analyze Signal Reflections?
- Improving Signal Quality
Reflections can cause signal degradation through distortion, ringing, overshoot and undershoot. Correcting these issues can reduce data errors and communication failure.
- Improving Data Transmission
The quality of data transmission can be improved by correcting timing issues caused by reflections including bit errors, degraded eye diagrams, jitter, and signal skew.
- Optimizing Performance
By analyzing signal reflections, you can mitigate crosstalk, signal loss, and timing errors- ultimately optimizing signal performance.
- Verifying Design Parameters
Performing analysis during the design process will verify the PCB performs as intended once manufactured and validates the design against the required standards and specifications before compliance testing.
- Preventing EMI
Reflections can contribute to Electromagnetic Interference (EMI). Reflected signals can increase radiated emissions and interfere with other devices. Systems with significant reflections can become more susceptible to external noise which can further degrade performance. Analyzing and mitigating reflections will help reduce EMI and interference with other electronic systems.
Performing reflection analysis at any stage of the design is going to have benefits but having this as the last step in your design process can result in late-stage design changes, additional rework, and more design hours if any issues are found. Analyzing signal reflections throughout the PCB layout will allow you to find and improve signal quality while you are designing- this is where Sigrity Aurora can help.Analyzing Signal Reflections with Sigrity
Sigrity Aurora includes easy-to-use workflows that step you through the required procedure to analyze signal and power integrity in your PCB designs. The Reflections Workflow in Sigrity Aurora is commonly used to identify signal reflections in the PCB design, providing a step-by-step procedure to perform layout-based analysis directly within the PCB layout canvas. The reflections workflow can be used by PCB designers throughout the PCB layout process to identify and correct issues when change is easiest, reducing time spent on prototyping, troubleshooting, and redesigning the PCB. Sigrity Aurora streamlines the product development process and allows you to efficiently analyze signal reflections with:
- A unified environment for PCB design and signal integrity analysis
- Easy-to-use workflows
- Minimal setup and modeling
- Visual overlays directly on the PCB canvas with color-coded results
- Detailed, tabular results to easily pinpoint signal reflections
Learn more about reflection analysis and how to resolve issues using Sigrity Aurora with our free course: Introduction to In-Design SI/PI analysis with Sigrity Aurora.
