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Posted on Sep 29, 2015
EMA interviewed Mike Crittenden to learn about his experience with EDABuilder.
Posted on Sep 29, 2015
With the help of Cadence Software, VeriSilicon shortened their FPGA-based ASIC prototype development time by 75% and completed optimal pin assignment in one week vs. at least one month previously.
Posted on Sep 29, 2015
Tait Improves PCB Design Productivity by 30% Using Cadence Allegro Platform
Posted on Sep 29, 2015
Constraint-Driven High-Density Interconnect (HDI) PCB Design Flow Helps NVIDIA Speed Products to Market
Posted on Sep 29, 2015
Liquid computing leverages Allegro System Interconnect Design Platform to complete complex printed circuit board design.
Posted on Sep 29, 2015
IBM Accelerates Large-scale PCB System Design Using Unique Cadence Multi-style Design Entry Solution
Posted on Sep 29, 2015
A short customer success story about how one designer benefits from CircuitSpace's time saving capabilities.
Posted on Sep 29, 2015
Allegro FPGA System Planner helped JDSU achieve a 30% to 40% time savings in their front-end design process. In addition, they realized a 50% time reduction in routing high-speed signals.
Posted on Sep 29, 2015
Check out this success story about how Huawei achieved a 50% productivity boost in RF PCB post processing using the Cadence Allegro Platform and services.

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