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Posted on Nov 2, 2018
Measure from true signal origin to end point through vias and through packages, not just the etch, so you can get timing right and ensure signal performance.
Posted on Nov 2, 2018
Visual indicators of length constraints help you meet delay propagation and total etch length goals when placing components.
Posted on Nov 2, 2018
Real-time interactive checks help you easily find and fix common route quality issues that manufacturing DRC signoff checks miss.
Posted on Oct 19, 2018
Routing DDR and high-speed bus interfaces can be one of the most daunting tasks in your design. With the new bus designer, all you need to do is simply describe the bus you are trying route and Constraint Manager for OrCAD will handle generating the appropriate constraints automatically.
Posted on Oct 19, 2018
Remove unused sections of plated through holes in high-speed designs to improve signal integrity on your designs.
Posted on Oct 19, 2018
Easily meet length and phase pin-to-pin constraints as traces bend without creating electrical issues.
Posted on Oct 19, 2018
Easily and quickly identify impedance discontinuity issues visually, without simulation models or extensive signal integrity expertise.
Posted on Oct 19, 2018
Easily identify nets with inconsistencies between the signal and return paths and quickly find the cause in real-ime while you design without waiting for the SI engineer to perform analysis and provide feedback.
Posted on Oct 19, 2018
Post-design DFM checks are too late. Even if you’re able to find a mistake, you’re going to lose hours, days, even weeks adjusting your design. OrCAD gives you the full DFM, Design for Fabrication (DFF), Design for Assembly (DFA), and Design for Test (DFT) checks you need in real-time while you design, so you can complete your design fast and signoff with confidence.
Posted on Oct 15, 2018
Get help from the PCB design experts at EMA with the tips and tricks you need to achieve highspeed PCB design success.

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